Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.

Abstract: Structures and methods for testing a re-programmable logic block embedded in a one-time programmable fabric in a PLD. The re-programmable logic block is tested without using the one-time programmable resources needed for implementing user circuits, by including a multiple input signature register (MISR) circuit coupled to receive output data from the re-programmable logic portion of the PLD. In some embodiments, a tester operating at a first and lower clock frequency can be used to test a re-programmable logic block operating at a second and higher clock frequency. In some of these embodiments, the one-time programmable fabric is tested at the first clock frequency.

Abstract: One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

Abstract: An integrated circuit and a method for configuring programmable logic thereof are described. A data register and an address register are coupled to an array of memory cells of the integrated circuit. Address storage is configurable for storing an address associated configuration data targeted for being written to at least one defective memory cell of the array of memory cells. Data storage is configured to store the configuration data associated with the at least one defective memory cell. A controller is configured to cause the address to be loaded into the address register and the configuration data to be loaded into the data register. The controller is configured to maintain a write state for continually writing the configuration data to the array of memory cells responsive to the address during operation of the integrated circuit.

Abstract: An integrated circuit (IC) is disclosed having circuitry arranged in a plurality of columns. A column in the IC is essentially a series of aligned circuit elements of the same type that extends from a first edge of the IC to a second edge. In addition there may be a center column having circuit elements of different types.

Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.

Abstract: A method and system for optimizing computer source code is provided. Prior to compiling the source code, the code is analyzed to determine the occurrence of repeating patterns of code. The repeating patterns of code are replaced with a programming loop that executes a single instance of the pattern multiple times using appropriate array indices and loop increments. In this manner, source code size is reduced making transfer, storage and compiling more efficient.

Abstract: A programmable logic device may comprise a metric circuit operable to repeatedly perform a function and emit a first signal dependent upon its advancement into the function. A comparator may compare the first signal from the metric circuit to a predetermined reference signal. A controller may then selectively disable a portion of the programmable logic device dependent upon the results of the comparison. In a particular case, the weakened circuit may be a counter that repeatedly advances its count with a rate dependent upon an aging characteristic of a vulnerable element.

Abstract: Methods of estimating routing delays between two points in a programmable logic device (PLD). The invention takes advantage of the fact that there are a finite number of possible routes (routing paths) between any two points in a PLD. In PLDs with a regular and tiled structure, such as field programmable gate arrays, the number of routes between any two points that are likely to be used by the router is relatively small. Thus, given the locations of the two points to be connected, the route most likely to be used by the router can be determined, and an associated delay can be calculated. This associated delay is then reported as the estimated routing delay. This method of delay estimation can be much more accurate than using an average delay. When the delays between possible paths vary widely, the actual delay of a connection can vary widely from the average.

Abstract: A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

Abstract: A data density independent clock and data recovery system includes a lock phase adjust charge pump operably coupled to receive phase information and transition information from a phase detector and to produce a current signal, responsive to the phase information and transition information, to a loop filter that converts the current signal to a control voltage signal operably coupled to a voltage controlled oscillator that produces a clock signal to the phase detector based on the control voltage signal. The lock phase adjust charge pump includes a phase charge pump, a transition charge pump, a programmable DC bias current sink, and two programmable offset bias current sinks. The transition charge pump includes a programmable transition current sink. The control logic operates under external control to adjust the currents conducted by the transition charge pump, the programmable DC bias current sink, and the two programmable offset bias current sinks.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.

Abstract: Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.

Abstract: Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

Abstract: On-the-fly reconfiguration of a secured CPLD. In one embodiment, a CPLD includes a novel security circuit that provides two different security control signals: an EEPROM/SRAM security signal and an EEPROM security override signal. The EEPROM/SRAM security signal prevents reading from both the EEPROM and the SRAM, and also prevents writing to the EEPROM. The EEPROM security override signal enables reading and writing for the EEPROM even when otherwise disabled by the EEPROM/SRAM security signal, but is active only when a specific set of conditions are met. These conditions can include, for example, the application of a sufficiently long erase pulse to the EEPROM array. Thus, the security on the EEPROM array is overridden only after the configuration data set stored in the EEPROM array has been erased. Reading from the SRAM is not enabled by the EEPROM security override signal. Therefore, the configuration data set is not compromised.

Abstract: A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.

Abstract: Die probing devices can include multiple sets of probe wires, where certain probe wires correspond to test pads and other correspond to bond pads. The probe wires can be electrically coupled to each other using either a space transformer or a probe card, to provide appropriate continuity. Probe wires can generally be arranged in numerous different patterns depending upon (for example) pad layout, wire configuration, wire type, and probe head design/manufacturing constraints.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

Abstract: A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.