Abstract: A method and apparatus for creating run-time reconfigurable cores using a core template package. The core template package provides an object-oriented application programming interface for specifying run-time reconfigurable (RTR) electronic circuit designs in a RTR application program. A run-time parameterizable (RTP) core library includes a plurality of predefined RTP core classes that implement selected functions in an electronic circuit design when invoked from an RTR application program. An RTP core template package includes a plurality of template classes. Each template class has a predefined set of method interfaces and fields. The RTP core template package further includes an RTP core template class that includes methods for building, connecting and traversing a hierarchy of RTP core objects based on the template classes and the predefined RTP core classes.

Abstract: A multiplying phase detector includes a 1st multiplier, a 2nd multiplier and a phase error generation module. The 1st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1st clock, which is in-phase with the incoming stream of data and is one-half the rate of the incoming stream of data, to produce a 1st product. In this instance, the 1st product represents missing transitions in the incoming stream of data. The 2nd multiplier is operably coupled to multiply the 1st product with the incoming data stream to produce a modified stream of data. The phase error generation module is operably coupled to generate a phase error based on the modified stream of data and a 2nd clock, where the phase error represents a phase offset between the modified stream of data and the 2nd clock.

Abstract: Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block) located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

Abstract: An apparatus and method of the present invention includes a high frequency exclusive OR (XOR) with a peaked load stage. The peaked load stage coupled to the XOR produces a peaked response at a specified frequency of operation. The high frequency XOR comprises a mixer stage comprising first and second transconductance stages coupled to produce a differential output current. The peaked load stage receives the differential output current from the mixer stage and provides increasing impedance at a specified frequency of operation. The peaked load stage includes a pair of peaked load blocks comprising a saturation region peaked load MOSFET and a resistive load. The gate-to-source capacitance of the peaked load MOSFET is coupled to the resistive load to form a high pass filter that provides additional bias to a gate of the peaked load MOSFET that increases the resistance of the peaked load MOSFET at the specified frequency.

Abstract: A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates an error value based on the snapshots. The tapped delay line module produces the output clock based on the error value.

Abstract: Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.

Abstract: Ground bounce noise in a digital system is evaluated using a weighted average simultaneous switching output (“WASSO”) on an I/O bank of a digital switching device, such as a field programmable gate array (“FPGA”). The WASSO allows a designer to normalize output drivers having different characteristics on a single I/O bank. In a further embodiment, a simultaneous switching output allowance (“SSO allowance”) is calculated using scaling factors derived from values assumed in the creation of published SSO information and predicted actual values of the device in a digital system that are not represented in tables of published SSO guidelines. The SSO allowance is used in conjunction with WASSO values of adjacent I/O banks to evaluate ground bounce for adjacent I/O banks.

Abstract: Digital frequency synthesizer (DFS) circuits and methods use counters to define the positions of the output clock edges. A clock divider divides an input clock by a positive integer to provide a divided clock. A first counter circuit counts for one divided clock period, and the count is provided to a timing circuit that generates two or more sets of intermediate values. Each set represents a set of intermediate points within a period of the divided clock. Based on a specified multiplication value, one set of intermediate values is selected. Utilizing the divided clock, the selected set of intermediate values, and a second counter running at the same frequency as the first counter circuit, an output clock generator provides an output clock having an initial pulse at the beginning of each divided clock period, and a subsequent pulse at intermediate points represented by the selected set of intermediate values.

Abstract: A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verification circuit to the block under test; enabling variable latency data transfers to the block under test; and verifying that the block under test is implementing the variable latency data transfer protocol. The method could be implemented to verify the operation of a memory controller of an FPGA, for example. According to another embodiment, a method enabling a multi-stage verification is disclosed. Finally, specific implementations of a verification circuit coupled to an on-chip memory controller of an FPGA are disclosed.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

Abstract: A system for reducing condensation during testing of an integrated circuit is disclosed. An exemplary embodiment includes two seals which close both ends of an enclosed channel formed when the load board is secured to the device tester. Clean dry air with a pressure greater than that of the environment is feed into the enclosed channel and is trapped because of the seals.

Abstract: A programmable, equalizing buffer is provided having feedback transistors used to vary the transfer function of the equalizing buffer, such that a low pass response of a transmission channel is substantially equalized. A zero in the buffer's transfer function is established by a conductive state of transistors caused by signal feedback. Multiple transistors establish increased flexibility for establishing the location of the zero, while a cascade of buffer stages provides a second order transfer function effective to cancel second order channel effects.

Abstract: A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or several sequential current discontinuities, and the voltage is measured with an on-chip ADC. Measuring the voltage within the semiconductor die, rather than measuring at external test points, provides a more accurate prediction of device operation. Multiple test points are measured using a multiplexer, multiple ADCs, or by reconfiguring an FPGA. Impedance versus frequency information of the greater power distribution system connected to the semiconductor die is obtained by transforming the voltage and current through the semiconductor die measured during a current discontinuity.

Abstract: Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes and corrupt the data state of the memory cell. Separating the half cells by at least two rows avoids corruption that could occur if diagonally arranged half cells were hit by a high-energy particle. In a particular embodiment, offset half cells are used at the top and bottom, respectively, of two adjacent columns of memory half cells.

Abstract: According to one embodiment a system is described. The system includes a direct memory access (DMA) controller and an input/output (I/O) device coupled to the DMA controller. The DMA controller is adaptable to operate in a normal mode and a descriptor mode.

Abstract: Method and apparatus for a system monitor (20) embedded in a programmable logic device (10, 50, 60) are described. The system monitor (20) includes a dynamic reconfiguration port interface (205) for configuring or reconfiguring the system monitor (20) during operation thereof. The system monitor (20) includes an analog-to-digital converter (200) which is reconfigurable responsive to input via a dynamic reconfiguration port (201).

Abstract: A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.

Abstract: A system and method for measuring the timing requirements of a sequential logic element of a programmable logic device. The sequential logic element has a first data terminal, an output terminal, and a clock terminal. A first synchronous element is coupled to the data terminal through a first delay element. The first synchronous element is clocked by a clock signal and receives an alternating test signal. A second synchronous element is coupled to the clock terminal through a second delay element of an input-output block. The second synchronous element is also clocked by the clock signal and receives the alternating test signal. The output terminal of the sequential logic element is monitored by a tester or by logic configured in the fabric of the programmable logic device to determine when the logic state changes as the delay of the first or second delay element is selectively varied.

Abstract: Method and apparatus for phase-timing compensation is described. More particularly, a clock source and a clock sink of a path are identified for phase-timing compensation for a design. An absolute path slack is obtained, and phase offset of the clock source relative to the clock sink is determined. A normalizing factor responsive to the phase offset is generated. A normalized slack is computed using the absolute path slack and the normalizing factor.