Abstract: Adjustment circuitry in a phase-locked loop (PLL) adjusts a sampling point to any desired location within a bit period of each bit of received high-speed serial data. The adjustment circuitry, responsive to program control, selectively adds current portions to a charge pump error current output thereby adjusting a feedback signal frequency to shift the serial data sampling point. A plurality of current mirror devices is scaled, with respect to a reference current device, to provide ?I current portions. A current control module controls the current portions magnitude and a sign of the current portions. The adjustment circuitry further controls charge pump programmable current sources in order to set a desired operating point of the PLL. The programmable current sources are controlled by a bias voltage and a plurality of selectable serial and parallel coupled resistors.

Abstract: A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated control signal. When the control signal is de-activated, the latch is de-coupled from the first voltage supply terminal and coupled to the non-volatile memory cell. If the non-volatile memory cell is programmed, the latch is coupled to a second voltage supply terminal, thereby storing a second logic value in the latch. If the non-volatile memory cell is erased, the latch is isolated from the second voltage supply terminal, and the first logic value remains stored in the latch. The latch can also be directly written through one or more access transistors, thereby facilitating testing.

Abstract: A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.

Abstract: An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

Abstract: A method and apparatus for providing a high speed buffer with high gain bandwidth and rail-to-rail operation is disclosed. Resistor-capacitor (RC) filters are added in current mirrors that are in the signal path. The effect of these filters is to create a frequency-dependent impedance that extends the gain bandwidth of the circuit.

Abstract: Method and apparatus for a bidirectional transceiver cell is described. Each bidirectional transceiver cell has a transmitter and a receiver, where the transmitter and the receiver share a phase-locked loop. The bidirectional transceiver cell is configured to act as either a transmitter or a receiver. The bidirectional transceiver cell is for multi-gigabit data rates.

Abstract: A system and method for diagnosing an electronic device remotely using a network is provided. The electronic device includes one or more programmable logic devices that are configurable. A diagnostic microcontroller functions to communicate to the programmable logic devices and to communicate to the network. To diagnose the electronic device, communication is established to the network and to a diagnostic/repair center. The diagnostic/repair center selects diagnostic commands and transmits them to the electronic device. The diagnostic microcontroller initiates the diagnostic commands on the one or more programmable logic devices to test their configuration and/or functionality. Test results are collected and transmitted back to the diagnostic/repair center for analysis. Based on the analysis, if appropriate, reconfiguration commands are sent to reconfigure the programmable logic device to correct identified errors.

Abstract: Described are various methods and systems for protecting proprietary configuration data for programmable logic devices. In one example, frames of configuration memory include overwrite-protect circuitry that reduces the risks associated with Trojan Horse attacks by preventing the overwriting of frames between device resets.

Abstract: Method and apparatus for processing data stored in a memory shared among a plurality of processors is described. In an example, a semaphore is provided that is associated with a first portion of the memory. Tasks are stored in the first portion of the memory, the tasks being respectively related to data segments stored in a second portion of the memory. A state of the semaphore is determined. Access among the plurality of processors to the first portion of the memory is controlled in response to the state of the semaphore. A task is executed to process a data segment of the data segments in response to a processor of the plurality of processors gaining access to the first portion of the memory.

Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is created. The graph representation includes nodes and edges. From the nodes in the graph representation, a plurality of register nodes are generated to correspond to respective register functions. Logic optimization is performed on nodes that represent combinational logic functions. For each register node and each output node, an evaluation equation is generated after performing logic optimization. For each clock cycle of a logic simulation, each evaluation equation is evaluated and produces an output value for the next clock cycle.

Abstract: Method and System for implementing a Finite State Machine (FSM) using software executed on a processor and having accurate timing information is described, where the accurate timing information is determined without the need to execute the software. An exemplary embodiment includes an IC having an embedded processor and a programmable logic fabric, where part or all of an FSM is implemented using assembly language code stored in a memory, for example, a cache memory, of the embedded processor.

Abstract: A flip-flop circuit includes a flip-flop, a first pass gate, a second pass gate, and a third pass gate. The first pass gate has an input to receive an input signal, an output coupled to the flip-flop's data input, and a control terminal to receive a first control signal. The second pass gate has an input coupled to the flip-flop's data input, an output coupled to the circuit's output, and a control terminal to receive a second control signal. The third pass gate has an input coupled to the flip-flop's data output, an output coupled to the circuit's output, and a control terminal to receive a third control signal. The first, second, and third control signals may be generated in response to various logical combinations of a bypass signal and a clock enable signal.

Abstract: Fast logic sharing is created using a feedback path from the output logic macrocell of one functional block to the product term inputs of another function block without going through an advanced interconnect matrix (AIM). The fast feedback path may be provided from the macrocell after the product terms XOR gate without registering, and/or after the register in the macrocell. The fast logic sharing avoids the slow AIM for feedback logic, and allows additional resources to be borrowed from other function blocks with a limited delay penalty. In particular, delay penalties resulting from dividing wide operations requiring multiple product terms between the product terms of multiple functional blocks are significantly reduced.

Abstract: Clock and data recovery (CDR) circuits that are fully digital. A data stream encoded with clocking information is passed through a tapped digital delay line. A phase and frequency detector coupled to the registered outputs of the tapped digital delay line determines the phase and frequency relationship between the recovered clock (DCO clock) and the transmit clock. A filter and control circuit then uses this information to generate a “servo” control signal, which is passed through a dither circuit and fed back to a digitally controlled oscillator (DCO). The circuit adjusts the DCO clock signal to match the transmit clock based on the value of this control signal.

Abstract: Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a “transfer bit”, is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient for correct programming, the transfer bit is read as “programmed”, and the data transfer continues. If the supply voltage is below the minimum supply voltage for proper programming, the transfer bit is read as “erased”, and the data transfer is reinitiated. In one embodiment, a second transfer bit set to the “erased” value is included in each word.

Abstract: Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.

Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Abstract: Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.

Abstract: A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD.