Abstract: A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a second set of signal lines to receive a grant associated with the data transfer request. A bus master unit (BMU) is coupled with the CSL through the first set of signal lines and the second set of signal lines. The BMU is connected to the CSI bus. The BMU arbitrates to take control of the CSI bus on behalf of the CSL enabling the CSL to perform data transfer to or from the CSI bus bypassing the processor.

Abstract: Structures and methods of representing programmable PLD hardware tiles including common routing resources common to all of the hardware tiles and unique logic resources unique to each hardware tile. A software representation of the programmable hardware tiles includes a common software tile including a description of the common routing resources, and, for each hardware tile, a unique software tile including a description of the unique logic resources included in the hardware tile. The common software tile has first terminals for coupling an instance of the common software tile to other instances of the common software tile, and also has second terminals. The unique software tile includes terminals for coupling the unique software tile to the second terminals of an instance of the common software tile. The software representation can also include a PLD device model that utilizes a uniform numbering scheme based on numbered instances of the common software tile.

Abstract: An asynchronous FIFO buffer communicates data between an input clock domain and a relatively slow output clock domain. The input clock frequency is not an even multiple of the output clock frequency, so the data transfer is asynchronous. The FIFO buffer includes a collection of input registers, a shift register, and some clock-comparison and write logic that controls the flow of data into, out of, and between these registers. The input data is loaded into the input registers in synchronization with the input clock. The clock-comparison and write logic compares the input and output clock signals and moves the data from the input registers to the shift register at an address value that may vary based on the result of the comparison of the input and output clock signals, skipping write cycles as necessary to avoid shifting data into the shift register faster than the data is shifted out.

Abstract: A decision feedback equalization (“DFE”) technique is suitable for use in a serializer-deserializer (“SERDES”) receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero (“RTZ”) data latch register. The RTZ data latch register has a first (“even”) series of RTZ data latches and a second (“odd”) series of RTZ data latches. A first even tap is coupled to the first even RTZ data latch and provides a feedback signal to the summing node on a first portion of a local clock cycle. A first odd tap is coupled to the first odd RTZ data latch and provides an odd feedback signal to the summing node on a second portion of the local clock cycle.

Abstract: Method and apparatus for designing custom programmable logic devices is described. In an example, a physical layout of programmable logic blocks is obtained. One or more dedicated logic blocks are then selected from a database. A physical size for each of the one or more dedicated logic blocks is obtained. A region within the physical layout for each of the one or more dedicated logic blocks is reserved in response to the respective physical size of each of the one or more dedicated logic blocks. Each or the one or more dedicated logic blocks is the positioned within the respective region reserved.

Abstract: A programmable logic device includes a block random access memory (“BRAM”) that is split into two first in, first out (“FIFO”) memory arrays. Two sets of FIFO control logic and FIFO ports are associated with a single BRAM so that the BRAM can be operated as memory buffers for two independent FIFO memory systems.

Abstract: Method, apparatus, and computer readable medium for determining signal routing cost within an integrated circuit is described. In an example, the integrated circuit is divided into topology units and includes routing resources. A respective span is determined in terms of one or more of the topology units for each of the routing resources. A cost value is assigned to each of the routing resources using the respective span associated therewith. A routing resource is selected from the routing resources. At least one distance between the routing resource and at least one other of the routing resources is calculated. A future cost value for the at least one distance is computed using the cost value assigned to the routing resource.

Abstract: A method and system for processing a plurality of multi-bit configuration words for configuring a programmable logic device. One or more of bits of the multi-bit configuration words are identified as “Don't Care” configuration bits that do not affect the functionality of the programmable logic device. These “Don't Care” configuration bits may or may not be related to the specific configuration of the programmable logic device. A lossy compression operation is performed on the multi-bit configuration words thereby creating a compressed data set. The identified “Don't Care” configuration bits are used during the compression operation. For example, the compression operation may include (1) maintaining a compression buffer of previously compressed configuration words, and (2) comparing configuration words to be compressed with the configuration words in the compression buffer, wherein the “Don't Care” configuration bits are deemed to result in matches during the comparison.

Abstract: Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller (1517) coupled to an analog-to-digital converter (200). An analog channel is selected for input to the analog-to-digital converter (200). Analog information is converted to digital information by the analog-to-digital converter (200), and then such digital information may be stored in data registers (209) for reading out via the boundary-scan controller (1517).

Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Abstract: A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

Abstract: An elastic buffer for buffering a stream of data blocks includes a controller and a memory space, wherein multiple data blocks can be written and read during a single write or read clock cycle, respectively. Multiple read addresses are used for each read operation, allowing read access to non-contiguous memory locations during a single read cycle when desired. Therefore, the elastic buffer can perform clock correction and channel bonding operations on data streams that include correction and alignment data block sequences that do not match the width of the memory space. A stagger bit can be used to indicate the timing of read address adjustments during clock correction and channel bonding operations.

Abstract: A method of producing a carrier wafer for an integrated circuit is disclosed. The method comprises the steps of providing a carrier wafer having a plurality of bump pads and a plurality of wire bond pads; providing a passivation layer on the carrier wafer; etching a passivation layer over at least a portion of the plurality of bump pads; applying solder bumps on the plurality of bump pads; and separately etching the passivation layer over at least a portion of the plurality of wire bond pads. An integrated circuit employing a flip chip is also disclosed.

Abstract: A configuration control circuit (400) allows a PLD to be quickly re-configured to implement different functions without requiring any configuration memory cells. The control circuit (400) includes a first input (IN1) connected to a first hardwired configuration bit (HCB1), a second input (IN2) connected to a second hardwired configuration bit (HCB2), an output (OUT) connected to one or more of the PLD's configurable elements (110), and a select circuit (402) to selectively connect either the first input (IN1) or the second input (IN2) to the output (OUT) in response to a select signal (SEL).

Abstract: A delay locked loop includes a primary delay line having a plurality of series-connected delay elements, wherein each of the delay elements operates in response to a supply voltage provided on a voltage supply line. When the delay locked loop is configured to operate in response to an input clock signal having a relatively high frequency, the voltage supply line is coupled to receive a first supply voltage. When the delay locked loop is configured to operate in response to an input clock signal having a relatively low frequency, the voltage supply line is coupled to receive a second supply voltage, which is significantly lower than the first supply voltage. When operating in response to the first supply voltage, the delay elements exhibit relatively short delays. Conversely, when operating in response to the second supply voltage, the delay elements exhibit relatively long delays.

Abstract: Method and apparatus for concatenated and interleaved turbo product code (TPC) encoding and decoding are described. Described are series concatenated and interleaved TPC encoders and decoders. One or more combinations of these encoders and decoders may be combined to provide a coder/decoder (CODEC). Such a CODEC may be used for communicating information between a computer and a network via a data channel.

Abstract: A semiconductor structure includes a carrier having a cavity formed in a top portion thereof, and a plurality of conductive contacts formed on a top surface of the carrier and positioned around the periphery of the cavity. A number of first coplanar dice are back-side mounted to a top surface of the cavity, and a number of second coplanar dice are flip-chip mounted to the first dice, wherein each of the first dice is electrically connected to two corresponding adjacent second dice to connect the dice in a cascade configuration. For some embodiments, selected dice are flip-chip mounted to the carrier. For other embodiments, selected dice are wire-bond connected to the carrier.

Abstract: An interface for an electronic device being coupled to an external device is provided. The interface includes a configurable hardware interface and a storage component for storing a bitstream that configures the configurable hardware interface to implement the driver of the external device. Specifically, the storage component can store one or more bitstreams that correspond to known drivers that can operate with the electronic device. The configurable hardware interface can include a programmable logic device (PLD), a memory, a control interface for controlling the PLD and the memory, and a synchronous communication interface for receiving information from the external device and enabling the control interface. The memory can list the device drivers (i.e. bitstreams) stored in the storage component and their respective addresses. The interface provides the advantage of storing any number of drivers in the device, thereby significantly reducing the time for the two devices to establish communication.

Abstract: A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.

Abstract: A multi-chip module comprising: a first IC having a first column of tiles, where each tile includes programmable logic; a second IC having a second column of tiles, where the second column is aligned with the first column; and a carrier die having signal lines, where a tile in the first column is directly connected to a tile in the second column via one of the signal lines.