Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

Abstract: Method and apparatus for a controller for dynamic configuration is described. The controller comprises a port interface, a read/write interface, and a plurality of flip-flops. The flip-flops, couple the port interface to the read/write interface. The port interface is configured to receive a plurality of signals, where portion of the plurality of signals are pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals. This facilitates reading and writing to storage elements at a rate which is at least approximately a frequency of the data clock signal while operating a device at approximately such frequency in which the controller is instantiated.

Abstract: Method and system for creating an electronic circuit design from a system-level environment. A plurality of user-selectable system-level design objects are provided in the system-level environment. Each system-level design object is defined by a system-level function and is selectable by a system-level designer. A plurality of hardware-level design objects are also provided. Each hardware-level design object is configured to generate a hardware definition of a hardware-level function. Each system-level design object maps to one or more hardware-level design objects. In response to selections made by the designer, a system-level design is instantiated in a system-level design file. The system-level design includes user-selected ones of the system-level design objects.

Abstract: A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (100) and identifying data input to each component specified in the language independent model to determine a latency for each component (220, 225). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (230). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself (235).

Abstract: Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.

Abstract: Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

Abstract: A calibrated VCO for use in a phase-locked loop includes a low frequency calibration block for setting a bias signal for a ring oscillator to a center point to prompt the ring oscillator to generate an oscillation that is in the middle of its output frequency range and a high frequency VCO gm stage for generating an adjustment calibration signal that is added or subtracted to and from the bias signal created by the low frequency calibration block. A low pass filter coupled between the gates of a current mirror of the low frequency calibration block operates to filter noise and interference generated within the low frequency calibration block. Additionally, the magnitude of the bias signal produced by the low frequency calibration block is significantly greater than the adjustment bias signal generated by the high frequency VCO gm stage.

Abstract: Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.

Abstract: A method (100) of physical circuit design can include the steps of packing components (110) of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations (115) to each component of the circuit design. The components of the circuit design can be clustered (120) by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed (125) to minimize critical connections. The circuit design can be declustered (130) to perform additional placer optimization tasks (135) on the declustered circuit design.

Abstract: Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide duplicate routing paths between source and destination of signals in the design. The duplicate paths are selected such that an SEU affecting one of the duplicate paths simply switches the signal between the two paths. Thus, if one path is disabled due to an SEU, the other path can still provide the necessary connection, and the functionality of the design is unaffected. The methods can be applied, for example, to routing software for field programmable gate arrays (FPGAs) having programmable routing multiplexers controlled by static RAM-based configuration memory cells.

Abstract: Methods of implementing a static memory cell compliant with the requirements of phase shift masks. A phase shift compliant memory cell is generated by implementing a single bit line, two word lines, first and second cross-coupled logic gates, and first and second pass gates. The logic gates and pass gates include transistors that use a fabrication layer (e.g., polysilicon) to implement the gate nodes of the transistors. All of these gate nodes extend substantially in a first direction. Throughout the static memory cell, the fabrication layer is implemented without T-shaped polygons in compliance with the requirements for a phase shift mask. In some embodiments, the static memory cell is a configuration memory cell for a PLD, and the method includes implementing an interconnection between at least one of the first and second storage nodes and programmable logic elements of the PLD.

Abstract: Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.

Abstract: Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

Abstract: An on-chip error correction circuit can be used to correct errors in memory cells of a FPGA. In one embodiment of the invention, the circuit can compute, during configuration, a plurality of error correction bits. These error correction bits are stored in a designated location on the FPGA. After all the memory cells are configured, the error correction circuit continuously computes the error correction bits of the memory cells and compares the result to the corresponding values stored in the designated location. If there is discrepancy, the stored error correction bits are used to correct the errors. In another embodiment of the invention, a plurality of parity bits of the original configuration bits is calculated. These parity bits are stored in registers. The FPGA contains on-chip parity bit generators that generate the corresponding parity bits. A discrepancy between the generated and stored parity triggers error correction action.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: A flexible architecture for nesting joint test action group (JTAG) test access port (TAP) controllers for FPGA-based embedded system-on-chip (SoC) is provided. Advantageously, a programmable approach permits bits in a selectable bit register (302) to be selected based on the number of JTAG TAPs that will be utilized. The selected bits can be used to vary the apparent length of an instruction register (302). Importantly, the flexible architecture permits access to any combination of a plurality of JTAG TAP controllers in the FPGA-based embedded SoC without the need to rewire any I/O pins of the FPGA and/or embedded IP cores.

Abstract: A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.

Abstract: A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several implementations in order to decrease delay in function implementation. The method describes techniques for estimating p-terms in a 2-bounded sub-graph, factoring methods, mapping strategies for LUTs and dedicated logic elements, and delay optimization of critical paths.

Abstract: Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.

Abstract: An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.