Abstract: A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second differential multiplexers coupled to the first differential multiplexers and configured to select second outputs from the first outputs; loop back signal lines configured to feed back the second outputs to at least part of the input clock signals of the first differential multiplexers; and differential signal lines of the differential clock tree coupled to the second outputs.

Abstract: Methods and systems are provided for dynamically compressing and decompressing a data stream in a manner that facilitates hardware implementation. In one aspect, a compression system identifies literal data sequences of variable length in the data stream and characterizes each literal sequence with an indicator that is inserted into the data stream. Sequences that repeat previous sequences in the data stream are identified and replaced with codes characterizing the repeating sequence. Another aspect provides a decompression method and system for removing indicators inserted by the compression system and replacing codes in the data stream with the repeating sequences characterized by the codes.

Abstract: A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.

Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.

Abstract: Method and apparatus for signal reflection removal, such as echo cancellation, is described. Signal samples are delayed. The delays allow burst processing of consecutive samples of transmitting and receiving signals in a communication network, such as in a telephone communication system. As a result, there is tremendous reduction of memory bandwidth when compared to conventional sample-by-sample processing of signals. Echo cancellers described herein can be implemented in an FPGA. Echo in over a thousand channels can be cancelled using an FPGA and an external memory device. In embodiments for reflected signal cancellation, multiple stages of echo estimation are used.

Abstract: A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested physical blocks (pblocks). Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that pblock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.

Abstract: A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and columns of function blocks and input/output (I/O) blocks programmably interconnected by a de-centralized interconnect structure. The interconnect structure includes numbers of interconnect lines segmented into shorter lengths. Programmable multiplexer circuits couple the segmented interconnect lines to the function blocks and I/O blocks. Programmable switch matrices couple the segmented interconnect lines together into longer interconnect lines of the desired length.

Abstract: Method and apparatus for post-placement optimization of resources for connections is described. To optimize resource placement, search windows are generated responsive to driver and load components, as well as to a connection between the driver and load components. Adding in a straight-line path search window may be used as an alternative where a bypassed resource is to be relocated. Using connection-based optimization in combination with driver- and resource-based optimization results in improved optimization with negligible impact on runtime.

Abstract: A method for correcting antenna violations in high-density integrated circuits (IC) begins by determining location of an antenna violation within a layout of a high-density integrated circuit. The processing continues by determining an affected input of a cell of the high-density integrated circuit based on the location of the antenna error. The processing then continues by identifying an available charge protection element. The processing further continues by logically coupling the available charge protection element to the affected input of the cell.

Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Abstract: An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal having a first frequency. A dedicated logic circuit embedded within the programmable logic device is operable using a second clock signal synchronized with the first clock signal and having a second frequency, the second frequency being a multiple of the first frequency. An interface coupled between one or more of the programmable logic blocks and the dedicated logic circuit includes multiplexer circuitry to multiplex output signals produced by the one or more programmable logic blocks among input terminals of the dedicated logic circuit.

Abstract: Method and apparatus for reducing power consumption within a logic device is described. A logic device comprises a clock gate and a flip-flop. The clock gate includes a clock enable terminal and a clock terminal. The flip-flop includes an input terminal, an output terminal, and a configuration terminal. The flip-flop is coupled to the clock gate. The flip-flop is configurable to trigger on at least one of a rising edge and a falling edge of a clock signal. The clock gate controllably gates the clock signal coupled to the clock terminal.

Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the transistor gate.

Abstract: Described are methods and circuits for precisely measuring signal propagation delays between synchronous memory elements. The memory elements are configured as a down counter that produces a test signal with a test period that is some multiple of a clock common to the memory elements. When the signal path is sufficiently fast for data to transfer between the synchronous memory elements in a single clock cycle, the test period is one multiple of the clock period. However, when the signal path fails to pass either rising or falling edges between the synchronous memory elements in a single clock cycle, the test period is increased by one clock period, and when the signal path fails to pass both rising and falling edges in a single clock cycle, the test period is increased by two clock periods.

Abstract: Structures and methods of reducing the susceptibility of programmable logic device (PLD) configuration memory cells to single event upsets (SEUs) by selectively adding metal-to-metal capacitors thereto. By adding capacitance to storage nodes in a memory cell, the susceptibility of the memory cell to SEUs is reduced. However, the performance of the memory cell also suffers. In PLD configuration memory cells, performance is not the most important factor. Therefore, for example, SEU-reducing capacitors can be selectively added to the PLD configuration memory cells while omitting the capacitors from user storage elements (e.g., block RAM) within the PLD. Thus, performance of the user storage elements is not adversely affected. Further, the use of metal-to-metal capacitors is well-suited to the configuration memory cells of a PLD, because these memory cells typically have additional area available for the capacitors above the programmable logic elements controlled by the associated configuration memory cells.

Abstract: A pad pattern of a die includes first and second sets of elongated pads. The first set of elongated pads is interleaved with the second set of elongated pads. Each of the elongated pads has a bond pad area and a probe pad. Each bond pad area has a first constant width along a substantial portion thereof. Similarly, each probe pad area has a second constant width along a substantial portion thereof. The first constant width is greater than the second constant width. Each elongated pad in the first set has a first orientation. Similarly, each elongated pad in the second set has a second orientation, opposite the first orientation.

Abstract: A system for driving a differential signal on a signal line and converting the differential signal from a rail-to-rail differential signal to a small signal differential signal is described. An exemplary embodiment of the circuit includes a first programmable differential driver circuit receiving a differential input; a programmable delay circuit receiving the differential input and coupled to a second programmable differential driver circuit; and a summation circuit coupled to the first and second differential driver circuits.

Abstract: Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.

Abstract: A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. Optional methods to cover the silicon die enhance thermal performance of the package.