Abstract: A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language (100) and identifying a loop construct within the language independent model (705). A determination can be made as to whether the loop construct is bounded (725). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences 735). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique (740, 755).

Abstract: A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first current-handling terminal connected to the first output terminal (Q), a second current-handling terminal connected to the second output terminal (Qb), and a first control terminal connected to a clock signal (C). A second transistor has a third current-handling terminal connected to the first output terminal (Q), a fourth current-handling terminal connected to the voltage supply terminal (Vss), and a second control terminal connected to a first input terminal (X1) of the output stage. A third transistor (440) has a fifth current-handling terminal connected to the first output terminal (Q), a sixth current-handling terminal connected to the voltage supply terminal (Vss), and a third control terminal connected to the second output terminal (Qb).

Abstract: A hybrid interface apparatus including a fixed base including a contact-locking structure supporting several spring-based contact members, and a nesting member slidably positioned over the fixed base and having a central test area that includes an array of through-holes that are aligned with upper ends of the contact members. To facilitate testing of ICs including both relatively low-speed general-purpose I/O structures and new high-speed I/O structures, the contact members mounted on the contact structure include both low-cost, relatively high-inductance contact members for facilitating communication with the general-purpose I/O structures of the IC, and relatively expensive, low-inductance contact members for facilitating high-speed communications with the high-speed I/O structures of the IC.

Abstract: A method of post-implementation simulation of a hardware description language (HDL) net list file, that does not match a HDL design file from which it was synthesized, comprises the steps of: creating a remap file which translates ports between the HDL net list file and the HDL design file; and simulating the HDL net list file utilizing the remap file and a (HDL) test bench file created for pre-implementation simulation of the HDL design file. The method may be executed in an integrated software environment or a batch software environment.

Abstract: Method and apparatus for preparing a design in a high-level modeling system. Hardware description language (HDL) code is generated for one or more of a plurality of high-level subsystems in a high-level design tagged by the user for HDL code generation. Previously generated HDL code may be reused instead of generating new HDL code for each subsystem tagged by the user for HDL code reuse.

Abstract: Method and apparatus for incremental design is described. More particularly, a text-circuit description of the integrated circuit having logic groups of respective logic instances is obtained. Area groups are created for the logic groups and correspondingly assigned. Unchanged logic groups are guided on an incremental implementation from existing guide files, and changed logic groups are re-implemented in area groups corresponding to the changed logic groups. In this manner, runtime of the unchanged logic groups is reduced by an incremental guide implementation instead of a re-implementation, while performance of such unchanged logic groups is maintained from a prior implementation. Furthermore, degrees of freedom for re-implementing are enhanced for improving a design, as all prior mapping, placing and routing within a changed area group may be stripped for re-implementation.

Abstract: Systems and methods utilizing virtual input/output (VIO) modules in PLDS. One or more VIO modules are embedded in a PLD along with the user circuit to be controlled and monitored. The VIO module includes a control module that acts as a virtual input module for the user circuit, and can optionally include a status module that acts as a virtual output module for the user circuit. A bi-directional data interface is provided between the user circuit and the VIO modules, and between the VIO modules and a communication module. The communication module is coupled through input/output pads of the PLD to an external communication link, and hence to a host computer in which resides software that controls the communication link. Thus, by interfacing with the host computer, a user can control the user circuit via the control modules and monitor output signals from the user circuit via the status modules.

Abstract: Method and apparatus for hardware co-simulation clocking is described. More particularly, single-step clocking is used to load one or more test vectors and to output test results from such test vectors after processing. The test vectors are processed with the hardware using a free-running clock, for example to speed up test time and to generate information related to operational speed. A simulation of the hardware is used, where single-step clocking out the test results facilitates verification of the hardware test results with simulation test results.

Abstract: Methods and apparatus are disclosed for compiling high-level blocks of an electronic hardware design in a high-level modeling system (HLMS) into hardware description language (HDL) components. Clock requirements are established, along with (optionally) explicit connections from implicit connections between the high-level blocks. In one pass through the high-level blocks, HDL components are generated that are consistent with the clock requirements and explicit connections, if any.

Abstract: A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

Abstract: Data is transferred on a field programmable gate array (FPGA) by (1) retrieving a first set of data from a first block RAM column of a configuration memory of the FPGA, (2) storing the first set of data retrieved from the first block RAM column in a frame data output register, (3) transferring the first set of data from the frame data output register directly to a frame data input register through a configuration bus of the FPGA, and (4) transferring the first set of data from the frame data input register to a second block RAM column of the configuration memory. The configuration bus is wide (e.g., 32-bits), thereby resulting in a high data transfer bandwidth.

Abstract: A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. Sixty-four write control circuits are coupled to the 64 memory cells. A first write address decoder receives a first subset of the six input signals, and in response, provides a first set of write select signals to the 64 write control circuits. A second write address decoder receives a second subset of the six input signals and a write clock signal, and in response, provides a plurality of decoded write clock signals to the sixty-four write control circuits. A write data value, which is applied to each of the write control circuits, is written to one of the memory cells in a synchronous manner with respect to the write clock signal in response to the first set of write select signals and the decoded write clock signals.

Abstract: A method and apparatus for calibrating a current source to a reference current through the use of 1-bit current comparisons. A temporary current source is first calibrated to the reference current, which allows an input offset current generated by the current comparator to be memorized. The current to be calibrated is then fine-tuned to the temporary current within specified limits, which effectively cancels comparison error that is generated by the input offset current.

Abstract: A method of enabling a hardware module to interact with a data structure is disclosed. The method comprises the steps of enabling the hardware module to determine an address of a data item referenced by the data structure; providing a base address for the data structure to the hardware module; and accessing a data item referenced by the data structure. A field programmable gate array having a hardware module capable of interacting with a data structure is also described. The field programmable gate array comprises a memory having a data structure; a hardware module coupled to the memory and comprising a lookup table; and a target address generated by the hardware module for a data item of the data structure.

Abstract: A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD.

Abstract: Within a computer automated tool, a method of physical circuit design can include assigning initial locations to components in the circuit design and determining an initial routing of connections between components in the circuit design using an overlap mode. The method also can include determining timing critical connections and selectively relocating components with at least one timing critical connection prior to performing a detailed routing of the circuit design.

Abstract: Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is included between each memory cell and the corresponding data input terminal of a first multiplexer. Each function select multiplexer has a first data input terminal coupled to the corresponding memory cell, a second data input terminal coupled to an external input terminal, and a select terminal controlled by a value stored in a function select memory cell. When a first value is stored in the function select memory cell, the programmable circuit functions in the same fashion as a known LUT. When a second value is stored in the function select memory cell, the programmable circuit functions as a wide multiplexer, with the data input values being provided by the external input terminals.

Abstract: A counter-controlled delay line for delaying signals having a wide range of possible frequencies is described. The counter-controlled delay line receives an input clock and produces a delayed output clock based on a delay select control signal. The delay select control signal includes three granularities of delay: a coarse grain, medium grain, and fine grain. The coarse grain delay is provided by a counter. The medium grain delay is provided by a sequential starter circuit coupled to an oscillator. The fine grain delay is provided by a trim unit.

Abstract: A flexible architecture for extending the instruction set for a boundary-scan interface. An instruction can be selected from a memory store (308) and decoded by a decoder (310). The instruction can subsequently be shifted into an instruction register (349) where it can be executed. Alternatively, a length of an existing instruction register (382) of a boundary-scan interface can be programmably appended to effectively increase the length of the register. A plurality of serially arranged bit registers (376, 378, 380) can be connected in series with the existing instruction register. By selecting an outer one of the serially arranged bit registers, the length of the existing instruction register can be extended.

Abstract: A systematic method for calculating future cost is disclosed. Pre-routing is performed from a source node to other nodes through a series of neighboring nodes. At each node in the pre-routing, the cumulative routing cost and Manhattan distance are calculated. This cumulative routing cost is used as a new future cost for a specific distance if it is lower than or there is no existing future cost for that distance. A table can be used to store the future cost data. During routing, the recorded future cost is added to the cumulative cost of a node to help guide the routing, improving router run-time.