Abstract: A phase matched clock divider includes a first feed-through flip-flop that receives a first input clock signal, and in response, provides a first output clock signal having the same frequency. The first feed-through flip-flop is enabled and disabled in response to a first reset signal. A plurality of series-connected flip-flops each receives the first input clock signal, and in response, provides a divided output clock signal. Each of the series-connected flip-flops is enabled and disabled in response to a second reset signal. The first and second release signals asynchronously disable the associated flip-flops in response to a third reset signal. The first release signal synchronously enables the first feed-through flip-flop in response to the third reset signal and a release clock signal. The second release signal enables the series-connected flip-flops in response to the third reset signal and a release control signal.

Abstract: Methods for utilizing PLDs with localized defects. Each PLD has a unique identifier. In one embodiment, a PLD provider tests a series of PLDs, selecting those having localized defects and recording the location of each detected defect for each defective PLD in a defect database. On receiving an identifier from a user, the PLD provider provides to the user the location information for the defects associated with the identified PLD. The data can be received and provided, for example, over the Internet. In one embodiment, the PLD provider implements the design based on the defect locations and provides the resulting design file to the user. In some embodiments, an incremental compilation is performed. The methods of the invention can also be applied to other device-specific information, such as information on the speed of critical sub-components of the PLD.

Abstract: A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.

Abstract: Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a permanent basis, and methods of converting a PLD to an OTP device. In some embodiments, only the erase function is disabled in the device. Because programming data cannot then be erased from the device, the addition of new programming data is very unlikely to yield an operable design. Therefore, the programming function is also effectively disabled. The programming function can be directly disabled in addition to or instead of the erase function, if desired. The erase and/or programming functions can be disabled, for example, by blowing one or more fuses included in the erase and/or programming circuitry of the PLD.

Abstract: According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.

Abstract: Structure and method for updating a system that includes a memory and a programmable logic device (PLD) retains a default PLD configuration in the memory while a new configuration is being stored in the memory, and thus protect the system from failure in case an interruption occurs while the new configuration is being stored. If a power failure interrupts the storing process, the default PLD configuration is still in the memory and can be re-loaded into the PLD and used when the system is re-started to make a further attempt at storing the new configuration. Methods are also disclosed for storing in the memory a configuration for a new PLD before the original PLD is replaced so that system hardware can be updated with minimum effort and disruption, and for dividing a directory structure into protected and unprotected regions.

Abstract: Pseudo-differential multiplexer circuits and methods. The circuit input signals are provided to two similar multiplexers, one of which is driven by true signals and one by the complementary input signals. No matter what the values of the circuit input signals, at least one of the two multiplexers always selects a low value. Therefore, at least one of the two multiplexers has the capability of overcoming a value stored in an output circuit (e.g., a latch) coupled to the output terminals of the two multiplexers. Thus, even when neither multiplexer can provide a high signal at the full value of power high VDD, the output circuit provides the correct output value. The invention also encompasses methods of selecting between circuit input signals by utilizing a pseudo-differential multiplexing technique, e.g., utilizing multiplexer circuits similar to those described above.

Abstract: A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry coupled to the programmable interconnect circuitry. An array of programmable logic blocks is coupled to the interconnect circuitry. Each programmable logic block includes a plurality of programmable logic elements coupled to the interconnect circuitry. Each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions.

Abstract: A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

Abstract: A method for testing a multi-gigabit transceiver begins by configuring the multi-gigabit transceiver for testing. The processing continues by varying a performance aspect of the multi-gigabit transceiver to produce a varied multi-gigabit transceiver. The processing continues by providing an input test signal to the varied multi-gigabit transceiver. The processing further continues by monitoring an output of the varied multi-gigabit transceiver with respect to the input test signal to determine a level of signal integrity. The processing continues by determining when the level of signal integrity provides a desired performance margin. The processing continues by adjusting a programmable operational setting of the multi-gigabit transceiver when the level of signal integrity does not provide the desired performance margin.

Abstract: Described are small, efficient SRAM cells that are insensitive to read errors. SRAM cells in accordance with one embodiment include a pair of cross-coupled inverters extending between first and second bit nodes and a read amplifier extending from one of the first and second bit nodes to an associated bitline. During a read access to a given memory cell, the corresponding read amplifier isolates the bit nodes from the bitlines to prevent the voltage on bitline BL from disturbing data stored in the memory cell.

Abstract: A programmable logic device includes a block random access memory (“BRAM”) with an embedded first in, first out (“FIFO”) controller. Embedding the FIFO logic in silicon, rather than configuring it in the fabric of the programmable logic device, provides a reliable, high-speed asynchronous FIFO memory system.

Abstract: A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.

Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.

Abstract: SEU mitigation, detection, and correction techniques are disclosed.

Abstract: A single integrated circuit can be designed to include a processor core and one or more configurable peripheral devices selectable by a user. Because the peripheral device is configurable, the user can select only the features he/she needs in the integrated circuit. As a result, the peripheral devices included in the integrated circuit do not have to be flexibly designed in the same manner as commercially available peripheral devices. Consequently, they are easy to use.

Abstract: A voltage detector circuit such as a power up and/or brownout detector circuit (100) includes a comparator (102) having at least one of its inputs (104) coupled to a diode-connected transistor (108). The other input can include another diode-connected transistor (110) or a resistor divider (302). Optional compensation capacitors (118 and 120) can be added to the comparator output (116) to provide glitch compensation. Since comparator (102) only needs to output a high or low voltage level, the components that are used to build circuit (100) do not have to have very tight tolerances. Circuit (100) also can operate at very low voltages and consume low amounts of power.

Abstract: A method and apparatus for providing high common-mode rejection ratio (CMRR) in a single-ended CMOS operational transconductance amplifier is disclosed. A common-mode feedback boosts the OTA CMRR, while allowing integration of conventional OTA improvements.

Abstract: A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.

Abstract: A method of using hardware libraries in a programmable logic device is disclosed. In particular, the method generally comprises steps of detecting a hardware library when compiling a software program for the programmable logic device; and accessing hardware module information stored in the hardware library; inserting the hardware module information of the hardware library into a reference platform.