Abstract: A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

Abstract: As system components which are used to customize an FPGA-based embedded processor SoC are selected and configured, the actual or estimated resources can be immediately provided. A GUI (350) can facilitate display of resources utilized by any or all selected system components, resources available for use by unselected system components and the customized device resources. Resource conflict and configuration checks can be used to identify and resolve system component problems and design and specification requirements. Notably, any associated resource problems can be immediately identified and rectified.

Abstract: Method and apparatus for managing persistent data objects between persistent storage and memory. A plurality of the objects include one or more pointer values that reference other ones of the objects. Persistent storage pointer values in an object are swizzled to memory pointer values when the object is transferred from persistent storage to memory. The memory pointer values in an object to persistent storage pointer values are unswizzled when the object is transferred from memory to persistent storage. In generating a persistent storage address from a persistent storage pointer value, the persistent storage pointer value is multiplied by a selected multiplier.

Abstract: Apparatuses for binary priority encoding are described. A binary priority encoder (100, 100L) includes a data input bus (139), a first logic tree (110) coupled to receive data from the input bus (139), and a second logic tree (130) coupled to receive a portion of the data from the input bus (139). The first logic tree (110) is configured to provide a flag signal (154) indicating whether at least one bit of the data is active. The first logic tree (110) is configured to provide control signals. The second logic tree (130) is coupled to receive the control signals. The second logic tree (130) is configured to select first partial addresses from the portion of the data responsive to the control signals. The control signals are further provided to the second logic tree (130) as second partial addresses.

Abstract: It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method for generating a bitstream for storing an encrypted design begins by generating an unencrypted bitstream including bits representing the design and bits that control loading of the design. The bits representing the design are encrypted and are combined with the bits that control loading, which are not encrypted.

Abstract: Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.

Abstract: A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

Abstract: A method (400) of placing a circuit design can include the steps of identifying topological levels of a circuit design representation (415) and determining an arrival time for each input signal to a look up table within a circuit design representation (420). The propagation delay associated with each pin of the look up table can be identified (420) such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (435). The method can continue processing each look up table of an identified topological level (440) as well as each topological level of the circuit design representation (455).

Abstract: A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.

Abstract: Static memory cell circuits having a single bit line further include first and second word lines, first and second cross-coupled logic gates, and first and second pass gates. The first pass gate is coupled between the bit line and a first storage node at the output of the first logic gate, and has a gate terminal coupled to the first word line. The second pass gate is coupled between the bit line and a second storage node at the output of the second logic gate, and has a gate terminal coupled to the second word line. The bit line and one of the word lines can be used to selectively set or reset a given static memory cell, if desired, without affecting other memory cells along the word line. In some embodiments, the static memory cell is a configuration memory cell of a programmable logic device (PLD).

Abstract: A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.

Abstract: Binary hysteresis comparator circuits, methods, and applications. A binary constant defines a window within which a binary input can change its value without triggering the comparator circuit output signal. An exemplary binary hysteresis comparator circuit includes a comparator circuit, an adder circuit, and a multiplexer circuit. The comparator circuit compares two multi-bit input values. A first comparator input is provided by the multiplexer circuit, which selects either a first value or a second value, depending on the comparator output signal. The first and second values differ by the binary constant, which is added to or subtracted from a multi-bit circuit input value by the adder circuit. An increase (or decrease) of less than the binary constant is ignored. Some embodiments include an optional overflow prevention circuit that prevents the selected value from exceeding predetermined parameters.

Abstract: A configurable logic block (“CLB”) in a programmable logic device (“PLD”), such as a complex programmable logic device (“CPLD”) or a field programmable gate array (“FPGA”), routes a timing signal, such as an external clock signal, through the CLB to provide a selected delay. The timing signal is routed through selected fast or slow pins of look-up tables (“LUTs”) in the CLB. CLBs are widely available in the PLD, allowing many timing signals to be delayed, and can be configured to account for board-specific or component-specific delays.

Abstract: Within a computer automated tool, a method (400) of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying (405) a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining (410) an initial routing of the clock domain. The method also can include determining (420) a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (430). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode (455) allowing sharing of routing resources by different nets.

Abstract: An electronic business card has a memory storing presentation slide images, a display that displays the images, and a processing device that governs the display process. The card has input devices (pads or buttons such as FORWARD, BACK and INDEX) allowing the user to control the display. The display's picture elements are preferably implemented as multi-chromic beads whose respective physical orientations are controlled by the processing device so as to form the viewed image. A method requires a target audience member to view at least one “payload” image (information that a presenter desires to propagate among a target audience), in association with at least one “hook” image (a quiz or game), on an electronic business card, PDA, or PC. The method includes presenting the payload image in association with the hook image, receiving and analyzing a user response, and displaying a reward image if the user response satisfies a criterion.

Abstract: According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.

Abstract: Methods for utilizing PLDs with localized defects. Each PLD has a unique identifier. In one embodiment, a PLD provider tests a series of PLDs, selecting those having localized defects and recording the location of each detected defect for each defective PLD in a defect database. On receiving an identifier from a user, the PLD provider provides to the user the location information for the defects associated with the identified PLD. The data can be received and provided, for example, over the Internet. In one embodiment, the PLD provider implements the design based on the defect locations and provides the resulting design file to the user. In some embodiments, an incremental compilation is performed. The methods of the invention can also be applied to other device-specific information, such as information on the speed of critical sub-components of the PLD.

Abstract: Pseudo-differential multiplexer circuits and methods. The circuit input signals are provided to two similar multiplexers, one of which is driven by true signals and one by the complementary input signals. No matter what the values of the circuit input signals, at least one of the two multiplexers always selects a low value. Therefore, at least one of the two multiplexers has the capability of overcoming a value stored in an output circuit (e.g., a latch) coupled to the output terminals of the two multiplexers. Thus, even when neither multiplexer can provide a high signal at the full value of power high VDD, the output circuit provides the correct output value. The invention also encompasses methods of selecting between circuit input signals by utilizing a pseudo-differential multiplexing technique, e.g., utilizing multiplexer circuits similar to those described above.

Abstract: A method for testing a multi-gigabit transceiver begins by configuring the multi-gigabit transceiver for testing. The processing continues by varying a performance aspect of the multi-gigabit transceiver to produce a varied multi-gigabit transceiver. The processing continues by providing an input test signal to the varied multi-gigabit transceiver. The processing further continues by monitoring an output of the varied multi-gigabit transceiver with respect to the input test signal to determine a level of signal integrity. The processing continues by determining when the level of signal integrity provides a desired performance margin. The processing continues by adjusting a programmable operational setting of the multi-gigabit transceiver when the level of signal integrity does not provide the desired performance margin.

Abstract: A series capacitor coupling (SCC) structure is controllable to capacitively couple a data input lead of the SCC structure to an output lead of the SCC, or to de-couple the data input lead from the data output lead. An SCC is controlled by a control bit stored in an associated memory cell. A multiplexer is fashioned out of a plurality of such SCC structures such that the edges of a digital signal received on a selected one of a plurality of multiplexer data input leads is coupled through the SCC structures onto an intervening node. The edges of the digital signal on the intervening node are then latched to recreate the incoming digital signal and the latched signal is output onto a multiplexer data output lead. The multiplexer is very fast and has a low leakage current in comparison to conventional transmission gate multiplexers used in programmable logic devices.