Patents Assigned to Xilinx, Inc.
  • Software defined subsystem creation for heterogeneous integrated circuits
    Patent number: 11188684
    Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 30, 2021
    Assignee: Xilinx, Inc.
    Inventors: Gangadhar Budde, Shreegopal S. Agrawal, Siddharth Rele, Subhojit Deb
  • Multi-rank high bandwidth memory (HBM) memory
    Patent number: 11189338
    Abstract: Certain aspects of the present disclosure provide techniques for relate to electronic devices that are configured to implement multi-rank high bandwidth memory (HBM) memory. In one aspect, an electronic device includes a chip that includes an interface circuit. The interface circuit is connected to first exterior pads. The first exterior pads have a first number of first data input/output exterior pads and a second number of clock enable output exterior pads. The first number is a first integer multiple of a number of data signals per channel of high bandwidth memory (HBM), and the second number is a second integer multiple of a number of clock enable signals per channel of the HBM. The second integer multiple is greater than the first integer multiple.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 30, 2021
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • On-chip memory access pattern detection for power and resource reduction
    Patent number: 11188697
    Abstract: Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: November 30, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Rajeev Patwari, Nithin Kumar Guggilla, Ashish Sirasao, Krishna Garlapati
  • Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices
    Patent number: 11188312
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 30, 2021
    Assignee: Xilinx, Inc.
    Inventors: Akella Sastry, Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddharth Rele
  • Latch-based level shifter circuit with self-biasing
    Patent number: 11190172
    Abstract: Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 30, 2021
    Assignee: XILINX, INC.
    Inventors: Mayank Raj, Parag Upadhyaya
  • Gate induced drain leakage robust bootstrapped switch
    Patent number: 11190178
    Abstract: Examples described herein provide an apparatus having a circuit with a grounding circuit and a switch. The apparatus generally includes a gate induced drain leakage (GIDL) protection circuit coupled to the switch and to an output voltage. The GIDL protection circuit may include a switch protection circuit configured to maintain a drain voltage of the switch less than a first supply voltage (Vdd) when the circuit is in an OFF state; and a ground protection circuit configured to maintain a drain voltage of the grounding circuit less than the first supply voltage when the circuit is in an ON state.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 30, 2021
    Assignee: XILINX, INC.
    Inventors: Diarmuid Collins, Edward Cullen, Ionut C. Cical
  • Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) timing adjustment based on output statistics
    Patent number: 11190199
    Abstract: Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 30, 2021
    Assignee: XILINX, INC.
    Inventors: Kevin Zheng, David Freitas, Hsung Jai Im
  • Bias current variation correction for complementary metal-oxide-semiconductor (CMOS) temperature sensor
    Patent number: 11181426
    Abstract: A temperature sensor includes a current source to produce a first bias current and a second bias current, a plurality of diodes, and temperature estimation circuitry. The plurality of diodes includes at least a first diode to receive the first bias current and a second diode to receive the second bias current. The temperature estimate circuitry measures a first voltage bias across the first diode resulting from the first bias current and a second voltage bias across the second diode resulting from the second bias current, and estimates a temperature of an environment of the temperature sensor based at least in part on the first voltage bias and the second voltage bias. The temperature sensor further includes error detection circuitry to measure at least one of the first or second bias currents and determine an amount of error in the temperature estimate based at least in part on the measurement.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: November 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Edward Cullen, Umanath R. Kamath, John K. Jennings, Diarmuid Collins, Ionut C. Cical
  • On-chip memory block circuit
    Patent number: 11182110
    Abstract: A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Sagheer Ahmad
  • Analog input buffer
    Patent number: 11183992
    Abstract: A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Roswald Francis, Bruno Miguel Vaz
  • Dual-driver interface
    Patent number: 11182317
    Abstract: A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel individually addressable by the network interface device and capable of carrying control data between the network interface device, the control data defining commands and the network interface being responsive to at least one command sent over the control channel to establish at least one additional data channel.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Steve Leslie Pope, David James Riddoch
  • Master latch design for single event upset flip-flop
    Patent number: 11177795
    Abstract: A master latch includes a latch input node and a latch output node, a first inverter with an input and an output, the input coupled to the latch input node and the output coupled to the latch output node, and a second inverter with an input and an output, the input coupled to the latch output node and the output coupled to the latch input node. The master latch further includes a first pull-up device connected between a source voltage and the latch input node, the first pull-up device configured to pull the latch input node up towards the source voltage when the latch output node is low, and a first pull-down device connected between the latch input node and a ground voltage, the first pull-down device configured to pull the latch input node towards the ground voltage when the latch output node is high.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 16, 2021
    Assignee: XILINX, INC.
    Inventors: Jun Liu, Bruce Young
  • Electro-static discharge (ESD) damage self-test
    Patent number: 11177654
    Abstract: Examples described herein provide a circuit and methods for self-testing to detect damage to a device, which damage may be caused by an Electro-Static Discharge (ESD) event. In an example, an integrated circuit includes an input/output circuit, an ESD protection circuit, and a system monitor. The input/output circuit has an input/output node. The ESD protection circuit is connected to the input/output node. The system monitor has a driving/measurement node selectively connectable to the input/output node. The system monitor is configured to drive and measure a voltage of the driving/measurement node. The system monitor is further configured to determine, based on driving and measuring the voltage of the driving/measurement node, whether a damaged device is present. The damaged device is in the input/output circuit or the ESD protection circuit.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: November 16, 2021
    Assignee: XILINX, INC.
    Inventors: John K. Jennings, James Karp, Michael J. Hart
  • Unified data model for heterogeneous integrated circuit
    Patent number: 11176296
    Abstract: A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Pradip Jha, Brendan Matthew O'Higgins, Dinesh K. Monga, Bart Reynolds, Ryan Linderman
  • CMOS analog circuits having a triode-based active load
    Patent number: 11177984
    Abstract: A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Kevin Zheng, Chuen-Huei Chou, Hsung Jai Im
  • Configuring programmable logic region via programmable network
    Patent number: 11169822
    Abstract: Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 9, 2021
    Assignee: XILINX, INC.
    Inventors: Rafael C. Camarota, David P. Schultz
  • Detecting and reporting random reset faults for functional safety and other high reliability applications
    Patent number: 11169892
    Abstract: Embodiments herein describe a hardware solution where a reset monitor in an integrated circuit detects and reports unintentional resets. A glitch in a reset path can cause a logic block to initiate an undesired or unintentional reset. As a result, the local circuitry in the logic block resets which causes them to lose data and their current state. In the embodiments herein, the reset monitor can monitor the reset signals generated within the logic blocks in the circuit. The reset monitor can compare these reset signals to golden copies of the resets signals generated by the reset generator. If a reset signal generated within a logic block does not match the corresponding golden copy of the reset signal, the reset monitor determines that an unintentional reset has occurred.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 9, 2021
    Assignee: XILINX, INC.
    Inventors: Sarosh Azad, Akshay Shetty, Alex Warshofsky
  • Bridge supporting multiple interfaces access to subsystem
    Patent number: 11169945
    Abstract: A device includes a processor, an SBI, and a plurality of interfaces. The processor is configured to manage operations of the device. The SBI is coupled to the processor. The plurality of interfaces is associated with the SBI. The interfaces of the plurality of interfaces have different interface protocol from one another. The SBI is configured by the processor and the configuration of the SBI activates one interface of the plurality of interfaces at any given time. The active interface that is selected from the plurality of interfaces and a host have a same interface protocol. The active interface is configured to receive host data from the host. The SBI is configured to generate a flag for the processor in response to the active interface receiving the host data. The SBI is configured to transmit device data to the host.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: November 9, 2021
    Assignee: XILINX, INC.
    Inventors: Danny Tsung-Heng Wu, Roger D. Flateau, Jr.
  • Warpage reduction
    Patent number: 11164749
    Abstract: Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is deposited into the first trench.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 2, 2021
    Assignee: XILINX, INC.
    Inventors: Nui Chong, Hui-Wen Lin
  • Network interface device
    Patent number: 11165720
    Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 2, 2021
    Assignee: XILINX, INC.
    Inventors: Steven L. Pope, Dmitri Kitariev, Derek Roberts