Abstract: An amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, and an output node. The first capacitor is electrically connected between a first power supply node and a first node, the second capacitor is electrically connected between the first node and a second node, the third capacitor is electrically connected between a second power supply node and a third node, and the fourth capacitor is electrically connected between the third node and a fourth node. The first transistor has a gate node electrically connected to the second node, and the second transistor has a gate node electrically connected to the fourth node. The output node is selectively connected to the first transistor and the second transistor. The first node and the third node are configured to be selectively electrically connected to a voltage node and a common voltage node.

Abstract: A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.

Abstract: A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application (using software code) and to the accelerator (using RTL). The embodiments herein describe a software defined approach where shared interface code is used to express both sides of the interface between the two heterogeneous systems in a single abstraction (e.g., a software class).

Abstract: A disclosed circuit arrangement includes a bus interface circuit and a configuration storage circuit coupled to the bus interface circuit. The bus interface circuit stores first error data in the configuration storage circuit in response to detection of an error condition. A second storage circuit provides storage of data, and an error re-logging circuit is coupled to the configuration storage circuit and to the second storage circuit. The error re-logging circuit polls the configuration storage circuit for the first error data signaling detection of an error, and in response to the first error data signaling detection of an error, stores the first error data in the second storage circuit, and clears the first error data from the configuration storage circuit to remove the signaling of the detection of the error.

Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Abstract: An apparatus for determining a bit index for a parity bit of a polar codeword is disclosed. Each index of a polar codeword may have an associated weight and an associated reliability value. The apparatus may compare the weights and reliability values of a group of bit indices in parallel to determine a bit index of the group associated with the lowest weight and highest reliability value. Additional groups may be processed until all of the bit indices of the polar codeword have been examined and the bit index with the lowest weight and highest reliability value is identified.

Abstract: A chip package and method for fabricating the same are provided which utilize a cover having one or more windows formed through one or more sidewalls to provide excellent resistance to warpage while allowing access to an internal volume of the chip package. In one example, the chip package includes a package substrate, an integrated circuit (IC) die, and a cover disposed over the IC die. The cover includes a lower surface facing the IC die, an upper surface facing away from the IC die, a lip extending from the lower surface, and a first sidewall extending from a first edge of the upper surface to the bottom of the lip. The lip is secured to the package substrate and encloses a volume between the lower surface and the package substrate. The IC die resides in the volume. A first elongated window is formed through the first sidewall and exposes the volume through the cover.

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect.

Abstract: A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

Abstract: Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.

Abstract: Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.

Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.

Abstract: Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input signal from an input node. In some examples, the shield reference node may also include conductive traces disposed between the input node and/or the gate traces and a corresponding nearest reference potential node such that parts of parasitic capacitances in the input buffer may be shielded. Accordingly, the bandwidth of the input buffer may be advantageously improved. The high frequency return loss (S11) may also be improved accordingly.

Abstract: A circuit arrangement includes a memory circuit, data upload circuitry, data formatting circuitry, and a systolic array (SA). The data upload circuitry inputs a multi-dimensional data set and stores the multi-dimensional data set in the memory circuit. The data formatting circuitry reads subsets of the multi-dimensional data set from the memory circuit. The data formatting circuitry arranges data elements of the subsets into data streams, and outputs data elements in the data streams in parallel. The SA includes rows and columns of multiply-and-accumulate (MAC) circuits. The SA inputs data elements of the data streams to columns of MAC circuits in parallel, inputs filter values to rows of MAC circuits in parallel, and computes an output feature map from the data streams and the filter values.