Abstract: Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using homogeneous processing units. In the embodiments herein, the heterogeneous processing units can be arranged into a pipeline where each stage of the pipeline is performed by one of the processing units.

Abstract: An integrated circuit (IC) device includes a network device. The network device includes first and second network ports each configured to connect to a network, and an internal endpoint port configured to connect to first endpoint having a first processing unit and second endpoint having a second processing unit. A lookup circuit is configured to provide a first forwarding decision for a first frame to be forwarded to the first endpoint. An endpoint extension circuit is configured to determine a first memory channel based on the first forwarding decision for forwarding the first frame, and forward the first frame to the first endpoint using the determined memory channel.

Abstract: A method includes receiving a first and a second data from a first and second IO pad on a first and second data lines respectively. A data strobe is received from a third IO pad on a data strobe line. The first data and the second data are strobed based on the data strobe to generate a first and second strobed data. The first data from the first IO is received at the data strobe line and strobed based on the data strobe to form an another first strobed data and compared to the first strobed data to generate a comparison signal indicating whether adjustment to a delay of the first data line is needed. A delay command is generated to increase/decrease the delay of the first and second data line.

Abstract: Examples described herein provide for a technique for metal track routing with buffer bank insertion in a representation of a hardware design of an integrated circuit. In an example, pins of ports of hardblocks in a placed layout are identified. Logical tracks for nets associated with the pins of the ports are generated and assigned to respective metal layers. Logical tracks and corresponding nets are grouped into respective groups. Buffer bank(s) is inserted into the placed layout. Each buffer bank is for a group of logical tracks and divides each logical track and net of the group of logical tracks. Each buffer bank has pins associated with the respective divided nets. Each pin of the buffer bank(s) is assigned to a middle or higher metal layer. Metal tracks are generated in a representation of a hardware layout based on the logical tracks and pins of the ports and buffer bank(s).

Abstract: Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

Abstract: A data processing system has a poll mode driver and a library supporting protocol processing. The poll mode driver and the library are non-operating system functionalities. An application is provided. An operation system is configured while executing in kernel mode and in response to the application being determined to be unresponsive, use a helper process being an operating system functionality executing at user-mode to cause a receive or transmit mode of the application to continue.

Abstract: Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted configuration bitstream in a boot memory for the programmable integrated circuit.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.

Abstract: A reference voltage generator is disclosed. The reference voltage generator may include an operational transconductance amplifier (OTA), a bias generator, a first flipped voltage follower, a bias filter, a control signal filter, and a second flipped voltage follower. The OTA and the first flipped voltage follower may generate a control signal based on a reference voltage and a bias voltage from the bias generator. The bias filter may filter the bias voltage and the control signal filter may filter the control signal. The second flipped voltage follower may generate the output voltage based on the filtered bias voltage and the filtered control signal.

Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: The embodiments herein store tabulated values representing a linear or non-linear function in separate memory banks to reduce the size of memory used to store the tabulated values while being able to provide upper and lower values for performing linear interpolation in parallel (e.g., the same cycle). To do so, a linear interpolation system includes a first memory bank that stores the even indexed tabulated values while a second memory bank stores the odd indexed tabulated values. During each clock cycle, the first and second memory banks can output upper and lower values for linear interpolation (although which memory bank outputs the upper value and which outputs the lower value can vary). Using the upper and lower values, the linear interpolation system performs linear interpolation to approximate the value of a non-linear function that is between the upper and lower values.

Abstract: Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a decision feedback equalizer (DFE) in a digital signal processing system (DSP) may be then configured to have extra taps and corresponding expanded equalization ranges to mitigate the ISI. Thus, a deterministic ISI component at the N×Mth UI may be digitally corrected by providing equalization with N×M taps at low cost to facilitate scaling to higher bit rates.

Abstract: Methods and systems for parallelized encoding of video are disclosed. According to one embodiment, a video encoder comprises a plurality of encoding engines. Each encoding engine is configured to receive a respective designated region of a video frame and produce respective quantized coefficients, the respective region having one or more unencoded frame blocks. Each encoding engine has a local symcoder for performing entropy-based encoding of the respective quantized coefficients. The video encoder has a rate control module, in communication with each encoding engine, for receiving from the respective local symcoder of each encoding engine a respective region-level bit count. The video encoder has a central buffer, in communication with each encoding engine, for receiving from each encoding engine the respective quantized coefficients.

Abstract: A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the controller unit and a network and having a first medium access controller for connection to the network and a second medium access controller coupled to the data port of the controller unit, the accelerator module being configured to: on behalf of the software entity, process incoming data packets received from the network in one or more streams associated with a first set of one or more network endpoints; encapsulate data resulting from said processing in network data packets directed to the software entity; and deliver the network

Abstract: A data processing system is provided. A host processing device supports a host transport engine operable to establish a first transport stream over a network with a remote peer. Device hardware comprises a device transport engine. The device transport engine is configured to monitor the first transport stream to determine a state of the first transport stream and in response to an indication from the host processing device perform transport processing of the first transport stream.

Abstract: An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory channels and to the compute array. The IC further includes a controller configured to determine that each of the plurality of remote buffers has data stored therein and, in response, broadcast a read enable signal to each of the plurality of remote buffers initiating data transfers from the plurality of remote buffers to the compute array across the plurality of dies.

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.

Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.

Abstract: A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel individually addressable by the network interface device and capable of carrying control data between the network interface device, the control data defining commands and the network interface being responsive to at least one command sent over the control channel to establish at least one additional data channel.