Abstract: A circuit for merging streams of data to generate sorted output data is described. The circuit comprises a first input coupled to receive a first data stream having a first set of N values; a second input coupled to receive a second data stream having second set of N values; a routing circuit coupled to the first input and the second input, the routing circuit enabling the routing of the first set of N values of the first data stream and the second set of N values of the second data stream; and a comparator circuit coupled to receive each value of the first set of N values and the second set of N values from the routing circuit, the comparator circuit having N comparators, wherein each comparator of the N comparators is coupled to receive a value of the first set of N values and a value of the second set of N values. A method of merging streams of data is also disclosed.

Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate having transmitter for receiving a signal to be transmitted to a receiver of the substrate by way of a transmission channel; a first plurality of contacts adapted to receive a first integrated circuit die, wherein a contact of the first plurality of contacts is adapted to receive the signal to be transmitted by the transmitter; a second plurality of contacts adapted to receive a second integrated circuit die, wherein a contact of the second plurality of contacts is adapted to receive the signal transmitted by the transmitter and received by the receiver; a first resistive element coupled between a contact of the first plurality of contacts and the transmitter; and a second resistive element coupled between a contact of the second plurality of contacts and the receiver. A method of transmitting data in an integrated circuit is also described.

Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.

Abstract: Methods and apparatus are described for performing data-intensive compute algorithms, such as fast massively parallel general matrix multiplication (GEMM), using a particular data format for both storing data to and reading data from memory. This data format may be utilized for arbitrarily-sized input matrices for GEMM implemented on a finite-size GEMM accelerator in the form of a rectangular compute array of digital signal processing (DSP) elements or similar compute cores. This data format solves the issue of double data rate (DDR) dynamic random access memory (DRAM) bandwidth by allowing both linear DDR addressing and single cycle loading of data into the compute array, avoiding input/output (I/O) and/or DDR bottlenecks.

Abstract: A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.

Abstract: A scheduling system includes a request masking circuit configured to receive a plurality of original requests for priority arbitration among a plurality of entries, the plurality of original requests include a last original request and a first original request following the last original request. A last mask associated with a last grant result for the last original request is received from a mask generator circuit. A first masked request is generated by applying the last mask to the first original request. A request selection circuit is configured to generate a first selected request based on the first original request and the first masked request. The mask generator circuit is configured to generate a first mask based on the first selected request. The first mask is associated with a first grant result for the first original request.

Abstract: A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Abstract: Disclosed approaches for protecting against attacks on a network device, a second network device receives a first message from a first network device. In response to the first message, the second network device determines a first area from which the first network device issued the message. The second network device determines whether or not the first area intersects a second area having the second network device. In response to determining that the first area intersects the second area, the second network device acknowledges the first message to the first network device. In response to determining that the first area does not intersect the second area, the second network device rejects the first message.

Abstract: A voltage divider is described. The voltage divider comprises a pair of input nodes for receiving an input signal; a pair of output nodes configured to generate an output signal; a first capacitor having a first terminal coupled to a first output node of the pair of output nodes and a second terminal coupled to a second output node of the pair of output nodes; and a second capacitor having first terminal and a second terminal; a bypass switch having a first terminal coupled to the first terminal of the second capacitor and a second terminal coupled to the second terminal of the second capacitor; and a charge sharing switch coupled to the second terminal of the second capacitor; wherein the bypass switch and the charge sharing switch enable the sharing of charge between the first capacitor and the second capacitor.

Abstract: A netlist of a circuit design includes an interface portion and a main portion. The interface portion is decomposed into multiple levels. Each level specifies connections between a respective first set of circuit elements and a respective second set of circuit elements. The second set of circuit elements in each level, except a last level, includes the first set of circuit elements in a next level. The first set of circuit elements identified in a first level of the multiple levels have fixed locations. The second set of circuit elements in the multiple levels is placed-and-routed. The placing-and-routing of the second set of circuit elements in one level is completed before commencing placing-and-routing of the second set of circuit elements in the next level. The main portion is placed-and-routed after placing-and-routing the second set of circuit elements in the multiple levels.

Abstract: A network on a chip (NoC) testing interface (NTI) includes a plurality of switches whose ports are coupled to respective endpoints. In one embodiment, the ports and endpoints are coupled to a shared bus that starts and terminates at a root device. The endpoints are assigned unique address which the NTI uses to select one of the endpoints so that test data is forwarded to a device under test (DUT) coupled to the endpoint. In one embodiment, the endpoints include selection logic for determining whether the endpoint has been selected, and if so, forwarding test data to the DUT. For example, if the endpoint receives a data vector on the bus which has an address that matches the unique address of the endpoint, the selection logic forwards the test data contained in subsequently received data vectors to the DUT until a different address is received.

Abstract: Embodiments herein describe a SoC that includes a programmable NoC that can be reconfigured to support different interface communication protocols. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC (e.g., processors, memory, programmable logic blocks, etc.) to transmit and receive data using the NoC. The ingress and egress logic blocks may first be configured to support a particular communication protocol for interfacing with the hardware elements. However, at a later time, the user may wish to reconfigure the ingress and egress logic blocks to support a different communication protocol. In response, the SoC can reconfigure the NoC such that the ingress and egress logic blocks support the new communication protocol used by the hardware elements. In this manner, the programmable NoC can support multiple communication protocols used to interface with other hardware elements in the SoC.

Abstract: An example integrated circuit (IC) assembly includes: a substrate, and a first IC die stacked on a second IC die, a stack of the first IC die and the second IC die mounted to the substrate. The first IC die includes an active side, a backside, a plurality of through-silicon vias (TSVs) exposed on the backside, an electrostatic discharge (ESD) circuit on the active side, and metallization on the active side. The metallization includes a first plurality of metal layers disposed on the active side and a second plurality of metal layers disposed on the first plurality of metal layers, each of the second plurality of metal layers thicker than each of the first plurality of metal layers. The metallization further includes a U-route that electrically couples a first TSV of the plurality of TSVs to the ESD circuit, the U-route including a conductive path through the second plurality of metal layers.

Abstract: Physical synthesis for a circuit design can include determining, using a processor, a candidate net from a circuit design, wherein the candidate net spans a plurality of dies of a multi-die integrated circuit, and modifying, using the processor, the candidate net by performing physical synthesis resulting in a modified candidate net. The physical synthesis includes relocating a driver or a load of the candidate net or replicating the driver of the candidate net. An incremental routing can be performed on the modified candidate net using the processor. Further, the modified candidate net can be selectively committed using the processor based upon a timing analysis.

Abstract: Electrical circuits and associated methods relate to duty cycle correction having a voltage controlled delay line VCDL controlled by an analog voltage and a digital command signal to generate a VCDLout signal. In an illustrative example, the analog voltage may be generated by an analog circuit, the analog circuit may include a reference voltage, a low-pass filter, an amplifier and a loop filter. In an illustrative example, the analog circuit may be controlled by an analog command signal. The analog command signal may be programmable applied on the analog circuit to produce the analog voltage. The digital command signal may be programmable to select desired delay band in the VCDL. The analog voltage and the digital command signal may be applied to the VCDL together to obtain a desired duty cycle.

Abstract: Examples described herein provide a communication scheme between integrated circuit (IC) dies. In an example, an IC package includes a first IC die and a second IC die. The first IC die includes an encoder/decoder configured to implement encoded communications. The second IC die includes a transceiver configured to implement unencoded differential communications. The encoder/decoder is communicatively coupled to the transceiver. The encoder/decoder is configured to implement communications to the transceiver using a subset of a code map of the encoded communications.

Abstract: A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Abstract: An integrated circuit (IC) may include a scheduler for hardware acceleration. The scheduler may include a command queue having a plurality of slots and configured to store commands offloaded from a host processor for execution by compute units of the IC. The scheduler may include a status register having bit locations corresponding to the slots of the command queue. The scheduler may also include a controller coupled to the command queue and the status register. The controller may be configured to schedule the compute units of the IC to execute the commands stored in the slots of the command queue and update the bit locations of the status register to indicate which commands from the command queue are finished executing.

Abstract: Disclosed approaches for limiting use or a programmable IC involve a provider of programmable ICs generating, using one or more private keys of the provider, one or more signed configuration bitstreams from one or more circuit designs received from a customer. The provider changes the general purpose programmable IC into an application programmable IC that can only be programmed by the one or more signed configuration bitstreams. The application programmable IC and the one or more signed configuration bitstreams are provided from the provider to the customer.

Abstract: Apparatus(es) and method(s) for CDR are described. In a CDR circuit, there is a bang-bang phase detector (“BBPD”), a baud-rate phase detector (“BRPD”), a multiplexer, and a control circuit. The BBPD, configured to receive data and crossing samples, generates a first result indicating a first phase difference between data and crossing samples. The BRPD, configured to receive data and peak samples, generates a second result indicating a second phase difference between data and peak samples. The multiplexer is configured to select either such result as a phase-detect output for a mode of operation. A control circuit is configured to clear a metastable state: for receipt of the first detect result, check for dithering, determine a direction for phase adjustment responsive to detection of the dithering, and provide a phase adjustment in the direction; and for receipt of the second detect result, operate to use the second phase difference generated.