Abstract: A stacked wafer assembly and method for fabricating the same are described herein. In one example, a stacked wafer assembly includes a first wafer bonded to a second wafer. The first wafer includes a plurality of fully functional dies and a first partial die formed thereon. The second wafer includes a plurality of fully functional dies and a first partial die formed thereon. Bond pads formed over an inductor of the first partial die of the first wafer are bonded to bond pads formed on the first partial die of the second wafer to establish electrical connection therebetween.

Abstract: A network device includes a first port, a second port, and a traffic policer circuit. The traffic policer circuit is configured to provide a frame credit and a credit state associated with the frame credit, receive a start of a first frame of a first stream from the first port, and determine a first estimate frame length of the first frame based on the frame credit and credit state. After the first estimate frame length is generated and prior to an end of the first frame is received, the first frame is metered based on the first estimate frame length to mark the first frame with a first marking. After the end of the first frame is received, the frame credit and credit state are updated based on the first frame. The first frame is forwarded to the second port by policing the first frame based on the first marking.

Abstract: Disclosed approaches include inputting a block diagram representation of a circuit design to a processor. Respective high-level programming language (HLL) code fragments associated with each block of the block diagram representation are determined. A dependency graph is generated from the block diagram representation. One or more clusters of vertices are generated from the dependency graph. Each of the HLL code fragments represented by the vertices of each cluster includes a for-loop, and each cluster includes a subset of the plurality of vertices and edges. For each of the clusters, a plurality of for-loops of the HLL code fragments associated with blocks represented by the vertices of the cluster are combined into a single for-loop. An HLL function is generated from each single for-loop and the HLL code fragments associated with each block that is not represented by any of the one or more clusters.

Abstract: Methods and apparatus relating generally to synthesis are described. In such a method, a directed graph for a circuit design is generated. A cascaded chain is identified in the directed graph with a timing violation. A pipeline register stage of the cascaded chain is moved (or added) to remove the timing violation. The circuit design is transformed to provide a netlist including the pipeline register stage.

Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

Abstract: Apparatus and associated methods relate to a programmable resistor having a resistance iteratively programmed by a calibration control loop. In an illustrative example, the calibration control loop may alternately sample the programmable resistance and a reference resistance by producing a corresponding voltage drop across the resistors. The voltage drops may, for example, be induced by the same constant current source. The calibration control loop may compare the voltage drops with a comparator, for example. In some examples, the comparator may provide a count direction signal to a logic block, generating a calibration code. The calibration code may, for example, be applied to the programmable resistor, such that the resistance of the programmable resistor iteratively approaches the resistance of the reference resistor.

Abstract: Implementing a circuit design may include detecting, using computer hardware, a net of the circuit design with a hold timing violation, generating, using the computer hardware, a list including each load of the net, and filtering, using the computer hardware, the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing. Using the computer hardware, the circuit design is modified by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point.

Abstract: An example circuit includes: a transmitter configured to transmit a clock pattern based on a transmit clock; a receiver, coupled to the transmitter, configured to sample the clock pattern based on a receive clock to generate a bit pattern, where there is a non-zero frequency difference between the transmit clock and the receive clock; a phase interpolator (PI) configured to add a phase shift to a source clock to supply one of the transmit clock or the receive clock; and a test circuit configured to apply adjustments to the phase shift over a time period and determine a phase distribution of the PI based on changes in the bit pattern over the time period.

Abstract: An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.

Abstract: A circuit for extending the bandwidth of a termination block is described. The circuit comprises an I/O contact configured to receive an input signal; and a termination circuit coupled to the I/O contact, wherein the termination circuit comprises a plurality of trim legs coupled between a power supply and the I/O contact, each trim leg having a switch to control the impedance in the trim leg.

Abstract: A circuit for enabling the communication of data in a communication link associated with a data communication network is described. The circuit comprises a data generation circuit configured to receive a plurality of data streams and generate an output data stream; a control signal generator configured to generate synchronization headers; a serializer circuit configured to receive the output data stream from the data generation circuit and the synchronization headers from the control signal generator, wherein the serializer circuit generates, at an output, an output data signal having data of the output data stream and the synchronization headers; and a control circuit configured to control the data generation circuit and the control signal generator, wherein the control circuit enables a selection of the synchronization headers of the output data signal to enable channel alignment of the communication link.

Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET transistor is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the in and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second oxide isolation layer has a thickness greater than a thickness of the first isolation layer.

Abstract: Techniques related to a high bandwidth interface (HBI) for communication between multiple host devices on an interposer are described. In an example, the HBI repurposes a portion of the high bandwidth memory (HBM) interface, such as the physical layer. A computing system is provided. The computing system includes a first host device and at least a second host device. The first host device is a first die on an interposer and the second host device is a second die on the interposer. The first host device and the second host device are interconnected via at least one HBI. The HBI implements a layered protocol for communication between the first host device and the second host device. The layered protocol includes a physical layer protocol that is configured according to a HBM physical layer protocol.

Abstract: A crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, where the CFR module is configured receive the digital tilt filter output signal and perform a CFR process to the digital tilt filter output signal to generate a CFR module output signal at a CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the CFR module output, where the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Abstract: An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

Abstract: Various implementations of a multi-chip system operable according to a predefined transport protocol are disclosed. In one embodiment, a system comprises a first IC comprising a memory controller communicatively coupled with first physical ports. The system further comprises a second IC comprising second physical ports communicatively coupled with a first set of the first physical ports via first physical links, and one or more memory devices that are communicatively coupled with the second physical ports and accessible by the memory controller via the first physical links. The first IC further comprises an identification map table describing a first level of port aggregation to be applied across the first set. The second IC comprises a first distribution function configured to provide ordering to data communicated using the second physical ports. The first distribution function is based on the first level of port aggregation.

Abstract: Disclosed circuits and methods include N line buffers. Each line buffer is configured for storage of M data elements of a three-dimensional (3-D) input feature map (IFM). A request generator circuit is coupled to the N line buffers and to a memory configured for storage of the 3-D IFM. The request generator circuit is divides the 3-D IFM into a plurality of IFM sub-volumes based on values of N, M, and dimensions of the 3-D IFM. The request generator circuit reads from the memory, data elements at addresses of an unprocessed one of the IFM sub-volumes and stores the data elements of the unprocessed one of the IFM sub-volumes in the N line buffers. In response to a completion signal, the request generator circuit repeats the reading of an unprocessed one of the IFM sub-volumes and storing the data elements in the N line buffers.

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.

Abstract: Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.

Abstract: An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.