Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.

Abstract: An example capacitive digital-to-analog converter (CDAC) includes: a first plurality of capacitors consisting of M?1 capacitors, where M is an integer greater than one, the first plurality of capacitors including top plates coupled to a first node; a second plurality of capacitors consisting of M?1 capacitors, the second plurality of capacitors including top plates coupled to a second node; a first plurality of switches consisting of M?1 switches coupled to bottom plates of the respective M?1 capacitors of the first plurality of capacitors, the first plurality of switches further coupled to a third node providing a supply voltage and a fourth node providing a ground voltage; a second plurality of switches consisting of M?1 switches coupled to bottom plates of the respective M?1 capacitors of the second plurality of capacitors, the second plurality of switches coupled to the third node and the fourth node; and a control circuit including an input consisting of M bits for receiving an M bit code and an output c

Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.

Abstract: Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

Abstract: An example a method of optimizing a neural network having a plurality of layers includes: obtaining an architecture constraint for circuitry of an inference platform that implements the neural network; training the neural network on a training platform to generate network parameters and feature maps for the plurality of layers; and constraining the network parameters, the feature maps, or both based on the architecture constraint.

Abstract: A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.

Abstract: Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading by a quality of service management (QM) circuit, respective first data rate metrics and respective latency metrics from requester circuits while the requester circuits are actively transmitting memory transactions to a memory controller. The QM circuit periodically reads a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines, while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.

Abstract: An integrated circuit can include a slave processor configured to execute instructions. The slave processor can be implemented in programmable circuitry of the integrated circuit. The integrated circuit also can include a processor coupled to the slave processor. The processor can be hardwired and configured to control operation of the slave processor.

Abstract: Generating delays for a clock circuit includes, determining, using a processor, groups of contexts for exit points of the clock circuit based upon a plurality of characteristics and a type selected from a plurality of different types for each characteristic, forming, using the processor, sub-groups of the exit points based upon delay values for the exit points, and determining, using the processor, a mean delay value for each sub-group.

Abstract: A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer level testing of the functionality of the IC die. In one example, a wafer includes a plurality of IC dies. At least a first IC die of the plurality of IC dies includes a plurality of micro-bumps and a first temporary connection trace formed on an exterior surface of the die body. The plurality of micro-bumps includes at least a first micro-bump and a second micro-bump. The first temporary connection trace electrically couples the first micro-bump and the second micro-bump.

Abstract: An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.

Abstract: Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

Abstract: Monitoring signals in an integrated circuit can include monitoring a probed signal of an integrated circuit using a logic analyzer circuit implemented within the integrated circuit, detecting state changes in the probed signal using the logic analyzer circuit, and generating, within the logic analyzer circuit, a file specifying time stamped state changes of the probed signal.

Abstract: Emulating a heterogeneous application having a kernel designated for hardware acceleration may include compiling, using a processor, host program code into a host binary configured to execute in a first process of a computing system and generating, using the processor, a device program binary implementing a register transfer level simulator using the kernel. The device program binary may be configured to execute in a second, different process of the computing system. A high level programming language model of static circuitry of a programmable integrated circuit that couples to a circuit implementation of the kernel may be compiled into a static circuitry binary. The static circuitry binary may be used by the register transfer level simulator during emulation.

Abstract: Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.

Abstract: A circuit arrangement that includes master circuits generating access transactions, and each access transaction includes an address, a interconnect master identifier, and a system management master identifier. A slave circuit is coupled to the one or more master circuits and is configured to generate responses to the access transactions. Each response includes an interconnect master identifier from one of the plurality of access transactions. An interconnect circuit routes the access transactions to the slave circuit and routes the responses to the one or more master circuits according to the interconnect master identifiers. Exclusive access control circuitry controls exclusive access to the slave circuit based on the value of the system management master identifiers and addresses in the access transactions.

Abstract: An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.

Abstract: In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.

Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, the testing system includes a robot disposed in an enclosure and having a range of motion operable to transfer a chip package assembly between any of a first queuing station, a second queuing station and a plurality of test stations. The system also includes an automatic identification and data capture (AIDC) device operable to read an identification tag affixed to a carrier disposed in the first and second queuing stations, and a controller configured to control placement of chip package assemblies by the robot in response information obtained from a carrier disposed in at least one of the first and second queuing stations, the predefined test routine of the test processor of the first test station, and the predefined test routine of the test processor of the second test station.

Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.