Abstract: Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.

Abstract: Decompressing a data set includes inputting data units to a decompression circuit and comparing each input data unit to a run value and to a substitute value. In response to the data unit being not equal to the run value or the substitute value, the decompression circuit outputs the value of the input data unit; in response to the input data unit having the run value and a succeeding data unit having a value N not equal to zero or one, the decompression circuit outputs multiple data units having the run value based on the value N; in response to input data unit having the substitute value, the decompression circuit outputs one data unit having the run value; and in response to one input data unit having the run value and a succeeding data unit equal to zero or one, the decompression circuit outputs one data unit of the substitute value.

Abstract: Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.

Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.

Abstract: For generating code for simulation of a circuit design, a hardware description language (HDL) description and a high-level language (HLL) description of portions of the circuit design are input. The HLL description specifies a first function and the HDL description includes a call to the first function. A wrapper is generated for the first function. The wrapper has an associated stack frame and includes code that stores in the stack frame values of arguments specified by the call to the first function and code that calls the first function. An HLL simulation specification is generated from the HDL description. The HLL simulation specification includes a call to the first HLL wrapper in place of the call to the first function. The HLL simulation specification, the first HLL wrapper, and the HLL description are compiled into executable program code.

Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.

Abstract: Creating a platform architecture can include receiving, using a computer, user input specifying a plurality of attributes of the platform architecture, wherein the platform architecture is adapted for implementation in a system-on-chip, and determining, based on the attributes and using the computer, a processing domain of the platform architecture, wherein the processing domain includes a processor, a software operating context, a device, and a memory. A hardware description of the platform architecture is generated using the computer. The hardware description specifies the processing domain, wherein the operating context is adapted for execution by the processor, and the device and the memory are addressable by the processor.

Abstract: An integrated circuit (IC) includes a first device and a second device. A latency measurement circuit is configured to determine a first latency of the first device; and determine a second latency of the second device based on the first latency.

Abstract: Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-gm biasing to provide substantial immunity to process, temperature and voltage variations, for example.

Abstract: Reducing latency of a circuit design can include determining, using a processor, a set of sequential circuit elements of a circuit design that meets a condition for removal from the circuit design, wherein the condition is dependent upon a target technology process and a target operating frequency. Using the processor, a feasible cut for a selected sequential circuit element of the set is determined. The selected sequential circuit element and each other sequential circuit element of the set that is part of the cut is removed from the circuit design using the processor.

Abstract: Methods and circuits are disclosed for measuring temperature and/or voltage using ring oscillators. In an example implementation, temperature and/or voltage are determined using an iterative measurements of a ring oscillator. The ring oscillator oscillates with a different voltage-temperature response in each of the first, second and third modes. In each iteration, a first set of indications of frequency are determined for a ring oscillator in a first mode, a second mode, and a third mode. A coarse temperature estimate and a coarse voltage estimate of the ring oscillator are determined based on the indications of frequency measured in a first iteration. A more accurate temperature estimate and a more accurate voltage estimate of the ring oscillator are determined as a function of a second set of indications of frequency measured in a second iteration, the coarse temperature estimate, and the coarse voltage estimate.

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the compl

Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

Abstract: Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.

Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

Abstract: A system can include a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system can include a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

Abstract: Visualizing operations of a memory controller includes reading, using a processor, a plurality of commands of a memory controller from a data store, wherein the commands are associated with times of issue. Blocks are displayed for the plurality of commands upon a display device as a raster image. The blocks are ordered according to the times of issue of the commands represented by the blocks. The blocks are visually distinguished according to command type within the raster image.

Abstract: The disclosed approaches process a circuit design that specifies a clock signal. A plurality of wire segments of an integrated circuit (IC) are selected for a clock path to carry the clock signal. A delay of the clock path is determined based on delay values associated with identifiers of the wire segments and variation factors. Configuration data is generated from the circuit design once the delay of the clock path satisfies a timing constraint, and a circuit is generated from the configuration data to implement a circuit according to the circuit design.

Abstract: The disclosed circuit arrangements include a logic circuit, input register logic coupled to the logic circuit and including a first plurality of bi-stable circuits and a control circuit coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals from an input clock signal. The plurality of delayed clock signals include a first delayed clock signal and a second delayed clock signal. The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.

Abstract: An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.