Patents Assigned to Xilinx, Inc.
  • Stacked inductor structure
    Patent number: 9111675
    Abstract: An inductor implemented in an integrated circuit is described. The inductor comprises a plurality of loops of the inductor in at least a first metal layer and a second metal layer of a plurality of metal layers; and a plurality of vias connecting ends of loops of the plurality of loops in different metal layers; wherein each loop of the first metal layer which is connected to a corresponding loop of the second metal layer overlies the corresponding loop of the second metal layer. A method of implementing an inductor in an integrated circuit is also described.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: August 18, 2015
    Assignee: XILINX, INC.
    Inventor: Vassili Kireev
  • Method and system for forward error correction of interleaved-formated data
    Patent number: 9112529
    Abstract: In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 18, 2015
    Assignee: XILINX, INC.
    Inventors: Raied N. Mazahreh, Raghavendar M. Rao
  • LOW INSERTION LOSS PACKAGE PIN STRUCTURE AND METHOD
    Publication number: 20150222033
    Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 6, 2015
    Applicant: Xilinx, Inc.
    Inventors: Paul Y. Wu, Sarajuddin Niazi, Raymond E. Anderson, Suresh Ramlingam
  • Revision history storage and maintenance
    Patent number: 9098500
    Abstract: In one embodiment of the present invention, a method is provided for maintaining and storing revision history of a design. The method includes, in response to a first control input by a user, determining, by a processor, module definition parameters that have changed from a design file. The changed module definition parameters are stored in the design file. For each changed module definition parameter, revision data are appended to revision history data. The revision data indicates a revision identifier, a module definition parameter identifier, and an updated value of the changed module definition parameter.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: August 4, 2015
    Assignee: XILINX, INC.
    Inventors: Vasanth Asokan, Raj Nagarajan, Chukwuweta Chukwudebe
  • Find-first-set bit circuit and method
    Patent number: 9100015
    Abstract: Finding the first bit that is set in an n-bit input word includes generating n n-bit patterns from an n-bit input word. If the bit at one bit position of the input word has a logic 1 value, a corresponding pattern has a logic 1 value in a corresponding bit position and in each bit position left of the corresponding bit position, and a logic 0 value in each bit position right of the corresponding bit position. If the bit at the one bit position of the input word has a logic 0 value, the corresponding pattern has a logic 0 value in every bit position. The n patterns are combined into one merged n-bit pattern. An output n-bit pattern is generated from the merged n-bit pattern. The output pattern has a logic 1 value in one bit position that is the same as the rightmost bit position of the input word having a logic 1 value, and a logic 0 value in every other bit position.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: August 4, 2015
    Assignee: XILINX, INC.
    Inventors: Chuan Cheng Pan, Ashish Gupta, Siva Prasad Gadey
  • Configuration and testing of multiple-die integrated circuits
    Patent number: 9091727
    Abstract: In one embodiment, a configuration data sequence is input to a master programmable integrated circuit (IC). In response to control bits in the configuration data sequence, the master programmable IC transmits the configuration data sequence to one or more slave programmable ICs. The master programmable IC and the one or more slave programmable ICs are configured in parallel with configuration bits from the configuration data sequence.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 28, 2015
    Assignee: XILINX, INC.
    Inventors: Julian Lupu, Shivani C. Desai, Lee N. Chung, Teymour M. Mansour
  • On-the-fly technical support
    Patent number: 9092314
    Abstract: A method performed by an information handling system for on-the-fly technical support is described. In an exemplary method, an error message is read to obtain an error code therefrom. A project directory is searched to obtain a report; where the report indicates a failed module of a plurality of executable modules, and where the report is associated with the error message. A source of an error is identified from the error message. A failed stage of the failed module is identified from the report. A case inquiry for the error message is prepared for searching a document for resolution of the error, where the case inquiry identifies the failed stage. A network is accessed, and the case inquiry is sent over the network.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 28, 2015
    Assignee: XILINX, INC.
    Inventors: Debraj Roy, Achutha Rama Chowdary Alapati, Shrinivasraj Muddey
  • Memory interface circuit
    Patent number: 9092305
    Abstract: In one embodiment, a circuit for communicating with a memory is provided. The circuit includes a sorting circuit configured to receive a plurality of read and write transactions. The sorting circuit sorts the write transactions according to respective sizes of data to be written to the memory, and sorts the read transactions according to respective sizes of data to be read from the memory. A selection circuit is configured to select transactions for transmission to the memory, from the sorted read and write transactions, in an order that balances a quantity of data to be written to the memory over a first serial data link with a quantity of data to be read from the memory over a second serial data link. A transmitter is coupled to the selection circuit and is configured to transmit the selected transactions to the memory device on a serial data link.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: July 28, 2015
    Assignee: XILINX, INC.
    Inventors: Michaela Blott, Hamish T. Fallside
  • Differential level shifter for improving common mode rejection ratio
    Patent number: 9093987
    Abstract: A differential level shifter includes: a first PMOS transistor, wherein a source/drain of the first PMOS transistor is coupled to a first CMOS signal, a gate of the first PMOS transistor is coupled to ground, and another source/drain of the first PMOS transistor is coupled to a first output node; a second PMOS transistor, wherein a source/drain of the second PMOS transistor is coupled to a second CMOS signal, a gate of the second PMOS transistor is coupled to ground, and another source/drain of the second PMOS transistor is coupled to a second output node; and a shift component coupled between the first output node and the second output node.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 28, 2015
    Assignee: XILINX, INC.
    Inventor: Christopher M. Gorman
  • Circuit and method for testing jitter tolerance
    Patent number: 9088399
    Abstract: A transceiver circuit for self-test of jitter tolerance is disclosed. The transceiver circuit includes a transmitter circuit having an output coupled to an output terminal of the transceiver and a receiver circuit having in input coupled to an input terminal of the transceiver. The transceiver also includes a loopback path configured to provide a signal transmitted by the transmitter circuit to the input of the receiver circuit. The transceiver also includes a test control circuit that causes jitter to be introduced in the signal transmitted by the transmitter circuit when the test control circuit is operating in a self-test mode, but not when the test control circuit is operating in a non-test mode.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 21, 2015
    Assignee: XILINX, INC.
    Inventors: Leo Kar Leung Poon, David L. Ferguson
  • Digital signal processing block
    Patent number: 9081634
    Abstract: An apparatus is disclosed. This apparatus includes a digital signal processing (“DSP”) block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit (“ALU”) block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: James M. Simkins, Wayne E. Wennekamp, John M. Thendean, Adam Elkins, Richard L. Walke
  • Estimating system performance using an integrated circuit
    Patent number: 9081925
    Abstract: A method of estimating performance of a design can include selecting a segment of the design for hardware emulation within an emulation system implemented within an integrated circuit. The emulation system can include a generic accelerator coupled to a processor of the integrated circuit. The method further can include modifying the design, using a processor of a host system, to invoke the generic accelerator in lieu of executing the selected segment within the processor of the emulation system during emulation.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Paul R. Schumacher, Graham F. Schelle, Patrick Lysaght
  • Memory matrix
    Patent number: 9083340
    Abstract: An integrated circuit comprises a memory matrix including: a first memory cell array; a first multiplexer (MUX) coupled to an input of the first memory cell array; a second MUX coupled to an output of the first memory cell array; a second memory cell array; a third MUX coupled to an input of the second memory cell array; and a fourth MUX coupled to an output of the second memory cell array. The second MUX is coupled to the fourth MUX. The fourth MUX is configured to pass a selected one of: (1) an output from the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Ephrem C. Wu, Hongbin Ji, Rafael C. Camarota
  • Built-in integrated circuit debug design
    Patent number: 9083347
    Abstract: Circuits and methods for capturing internal signal values in a circuit before, during, and after a trigger event are disclosed. For example, a circuit can include a shift register configured to receive data values of an input data set over a plurality of cycles, and a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following the receiving of the trigger signal, where the trigger signal indicates a trigger event. The circuit can also include a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface and the shift register in response to receiving the trigger signal.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Rajesh Bansal
  • Parity check matrix
    Patent number: 9083383
    Abstract: An apparatus is disclosed. In this apparatus, at least one coder block has a parity check matrix. The parity check matrix comprises each element of an H matrix expanded by a Progressive Edge Growth (“PEG”) expansion factor and an Approximate Cycle Extrinsic Message Degree (“ACE”) expansion factor.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Nihat E. Tunali, Raghavendar M. Rao, Raied N. Mazahreh, Krishna R. Narayanan
  • Multi-die integrated circuit structure with heat sink
    Patent number: 9082633
    Abstract: An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventor: Douglas M. Grant
  • Throughput during high level synthesis
    Patent number: 9081930
    Abstract: Improving throughput during high level synthesis includes determining a data dependency for a flow control construct of a high level programming language description and translating the high level programming language description into a circuit design specifying circuitry for implementation within an integrated circuit. The circuitry is pipelined. As part of the circuit design and using a processor, a stall detection circuit is generated. The stall detection circuit is coupled to selectively initiate a stall of a stalling portion of the circuitry according to the data dependency.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Stephen A. Neuendorffer, Kecheng Hao, Guoling Han
  • Method and apparatus for physically unclonable function burn-in
    Patent number: 9082514
    Abstract: A method, non-transitory computer readable medium, and apparatus for performing physically unclonable function (PUF) burn-in are disclosed. For example, the method identifies, by a processor, a natural output of an integrated circuit before the integrated circuit is initialized, identifies, by the processor, a physical characteristic of the integrated circuit associated with the physically unclonable function, and ages, by the processor, the physical characteristic of the integrated circuit to burn-in the natural output of the integrated circuit.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventor: Stephen M. Trimberger
  • Configurable embedded memory system
    Patent number: 9075930
    Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: July 7, 2015
    Assignee: XILINX, INC.
    Inventors: Subodh Kumar, James M. Simkins, Thomas H. Strader, Matthew H. Klein, James E. Ogden, Uma Durairajan
  • Compilation of system designs
    Patent number: 9075624
    Abstract: A method is provided for compiling an HLL program. A command is input that indicates a set of HLL source files to be compiled and a set of functions in the HLL source files that are to be implemented on programmable circuitry of a programmable IC. For a source file including one of the set of functions, a respective netlist is generated from HLL code of each of the set of functions included therein. Interface code is also generated for communication with the netlist. HLL code of the set of functions in the HLL source file is replaced with the generated interface code. Each HLL source file is compiled to produce a respective object file. The object files are linked to generate a program executable on the programmable IC. A configuration data stream is generated that implements each generated netlist on the programmable IC.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 7, 2015
    Assignee: XILINX, INC.
    Inventor: Jorge E. Carrillo