Abstract: A method of providing an integrated graphical user interface can include responsive to executing a host computer program, displaying, within a graphical user interface of the host computer program, a visual element of a plug-in that executes in cooperation with the host computer program without loading a functional component of the plug-in within program execution memory of a computer system executing the host computer program. At least a portion of the functional component of the plug-in can be loaded within program execution memory responsive to a selection of the visual element.

Abstract: A system includes: an initial clock region; a first adjacent clock region adjacent to the initial clock region; a spine coupled to receive a clock signal from a clock; and a first phase detector coupled to detect a difference in phase between the initial clock region and the first adjacent clock region. The initial clock region comprises an initial delay element coupled to the spine and to the first phase detector.

Abstract: A data recovery unit includes a phase locked loop configured to receive data samples and generate an output; a first sample selector coupled to the phase locked loop; and an eye scanner coupled to the phase locked loop. The first sample selector is configured to receive the data samples and the output of the phase locked loop. The eye scanner comprises a second sample selector coupled to the phase locked loop via a first horizontal shift module.

Abstract: An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer.

Abstract: In one embodiment, a method for compiling an HDL specification for simulation of a circuit design is provided. Using one or more processors the circuit design is elaborated from the HDL specification. Two or more instances of a module of the elaborated design that have a same hardware configuration are determined. Simulation code that models the circuit design is generated. A first portion of the simulation code is configured to model the module having the hardware configuration. For each of the two or more instances, a second portion of the simulation code is configured to, in response to an indication to simulate the instance, execute the first portion of simulation code using a respective set of nets corresponding to the instance.

Abstract: A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system.

Abstract: A termination circuit configured to provide electrostatic discharge (ESD) protection is provided. Termination sub-circuits are coupled in parallel, each including respective pull-up and pull-down circuits. Each pull-up circuit has two transistors of a first type coupled in series between a data input and Vdd, a gate of one of the two transistors being coupled to a control input and a gate of the other one of the two transistors being coupled to a first enable input of the termination sub-circuit. Each pull-down circuit has two transistors of a second type coupled in series between the data input and Vss or ground, a gate of one of the two transistors being coupled to the control input and the gate of the other one of the two transistors being coupled to a second enable input of the termination sub-circuit.

Abstract: A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic sub-system includes programmable logic circuits configured to form a hardware portion of a user design. The processing sub-system includes processing circuits configured to execute a software portion of a user design. The safety sub-system is configured to perform a safety functions that detect and/or mitigate errors in circuits of the programmable IC. The safety sub-system includes hard-wired circuits configured to perform hardware-based safety functions for a first subset of circuits of the programmable IC. The safety sub-system also includes a processing circuit configured to execute software-based safety functions for a second subset of circuits of the programmable IC.

Abstract: A data recovery unit (DRU) includes: an oscillator; a phase detector unit configured to receive a reference phase and to receive input data through N wires, where N is an integer, to compare the reference phase with the input data to obtain phase errors, and to determine an average of the phase errors; a subtractor to subtract an output of the oscillator from the average of the phase errors to obtain an unbiased phase error; a delay unit to receive the input data; and a sample selector configured to receive an output from the delay unit and the output of the oscillator, and to output recovered data.

Abstract: An apparatus with package integrity monitoring capability, includes: a package having a die connected to an interposer through a plurality of bumps, wherein at least some of the bumps comprise dummy bumps; a package integrity monitor having a transmitter to transmit a test signal and a receiver to receive the test signal; and a first scan chain comprising a plurality of alternating interconnects in the die and in the interposer connecting some of the dummy bumps in series, wherein the first scan chain has a first end coupled to the transmitter of the package integrity monitor and a second end coupled to the receiver of the package integrity monitor.

Abstract: A programmable receiver of an integrated circuit is described. The programmable receiver comprises an input; a first programmable receiver circuit coupled to the input, wherein the first programmable receiver circuit has a first pull-up branch and a first pull-down branch and is controlled by a first enable circuit; a second programmable receiver circuit coupled to the input, wherein the second programmable receiver circuit has a second pull-up branch and a second pull-down branch and is controlled by a second enable circuit; and an output stage coupled to the first programmable receiver circuit and the second programmable receiver circuit, wherein the output stage receives an output of one of the first programmable receiver circuit and the second programmable receiver circuit. A method of implementing a programmable receiver in an integrated circuit is also disclosed.

Abstract: A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic circuits in the programmable logic sub-system are configured to form a set of circuits indicated in a set of configuration data. The processing sub-system also executes a software program included in the set of configuration data. The programmable logic sub-system and the processing sub-system are independently powered. In response to a power failure of the processing sub-system and continued power to the programmable logic sub-system, the safety sub-system resets only the processing sub-system. In response to a power failure of the programmable logic sub-system and continued power to the processing sub-system, the safety sub-system resets only the programmable logic sub-system.

Abstract: In a transmission line via structure, a plurality of sub-structures are stacked in a via through the substrate along a longitudinal axis thereof. Each of the sub-structures includes a center conductor portion, an outer conductor portion, and at least one dielectric support member. The center conductor portion extends along the longitudinal axis. The outer conductor portion is disposed around the center conductor portion. The dielectric support member(s) separate the outer conductor portion and the center conductor portion and provide a non-solid volume between the outer conductor portion and the center conductor portion. Conductive paste is disposed between the center and outer conductor portions of successive ones of the plurality of sub-structures to form an outer conductor and a center conductor.

Abstract: Processing a circuit design can include determining a first set of net sensitivity ranges for a net of the circuit design, wherein at least two net sensitivity ranges of the first set are partially overlapping, and translating the first set of net sensitivity ranges into a second set of net sensitivity ranges comprising a plurality of member net sensitivity ranges with no partially overlapping member net sensitivity ranges. A net sensitivity tree can be constructed that includes hierarchically ordered nodes. Each node can specify a net sensitivity range of one member of the second set of net sensitivity ranges.

Abstract: A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.

Abstract: An apparatus generally relating to a receiver is disclosed. In this apparatus, the receiver includes a phase interpolator, a detector and a slicer. The slicer is coupled to the phase interpolator to provide a sampling signal for a sampling position of the phase interpolator. The detector is coupled to the slicer to receive the sampling signal. The detector is configured to adjust a code of the phase interpolator to adjust the sampling position iteratively in response to the sampling signal to tune the sampling position of the receiver toward an optimum therefor.

Abstract: A programmable delay circuit block includes an input stage having a cascade input and a clock input, wherein the input stage passes a signal received at the cascade input or a signal received at the clock input. The programmable delay circuit block further may include a delay block configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the input stage and a pulse generator configured to generate a pulse signal having a pulse width that depends upon the amount of delay. The programmable delay circuit block also includes an output stage having a cascade output and a clock output. The output stage is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade output and pass the signal received at the clock input, the inverted version of the pulse signal, or the delayed signal from the clock output.

Abstract: One approach for authenticating data includes storing a plurality of combinations of representations of public keys and session key IDs in a non-volatile memory. A payload and accompanying public key, session key ID, and signature of the payload are input. The signature is a function of the payload and a private key of a key pair that includes the accompanying public key and the private key. Authenticity of the payload is determined based on the accompanying public key and session key ID and the combinations stored in the non-volatile memory, and from the signature and the payload. In response to determining that the payload is authentic, the payload is processed, and in response to determining that the payload is not authentic, processing of the payload is disabled.

Abstract: In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.

Abstract: A memory is disclosed that includes one or more TCAM memory units, each configured to store a respective set of rules. Each unit has an input coupled to receive an input search key from an input of the memory and includes a plurality of stages 1 through H. Each stage is configured to receive a respective multi-bit segment of the input search key and provide a result segment in response thereto. The result segment includes, for each rule of the respective set of rules, a bit that indicates whether or not the rule matches the segment of the input search key. Each unit also includes a first output circuit configured to generate a combined result indicating which rules match all of the respective segments received by each of the plurality of stages. The memory can also include one or more update circuits to update rules in a plurality of units.