Abstract: A method of processing a circuit design in a circuit design tool includes: identifying selection of a parameterized core to be instantiated in a description of the circuit design managed by the circuit design tool and configured for implementation in target hardware; processing a configuration file for the parameterized core to select a set of parameter values from a plurality of sets of parameter values dynamically based at least in part on the target hardware; creating an instance of the parameterized core in the circuit design having the selected set of parameter values; and implementing the circuit design for the target hardware.

Abstract: Approaches for verifying connectivity of signals in a circuit design include generating a configured version of the circuit design based on input parameter values. The configured version specifies connections from source pins of ports of circuit blocks of the configured version to destination pins of ports of circuit blocks. Expected source-destination connections between source pins and destination pins of the ports of the circuit blocks of the configured version are determined from the input parameter values. A connectivity checker that includes HDL code is generated based on the expected source-destination connections. For each of the expected source-destination connections, the HDL code forces a first signal value on a source pin of the expected source-destination connection in the configured version of the circuit design and determines whether or not a second signal value at a destination pin of the expected source-destination connection matches the first signal value.

Abstract: In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.

Abstract: In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit coupled to limit a tail current passing through the differential amplifier.

Abstract: In a method for channel adaptation, an analog input signal is received with a bimodal receiver via a communications channel. The analog input signal is converted to a digital input signal with an analog-to-digital converter of a digital receiver of the bimodal receiver. Channel coefficients are detected for the digital input signal associated with the communications channel. The channel coefficients indicate a number of post-cursor taps of the bimodal receiver to be used to provide an equalized digital output signal from the digital input signal. It is determined whether the number of post-cursor taps or a value associated therewith is equal to or less than a threshold number. A switch from the receiving of the analog input signal by the digital receiver to an analog receiver of the bimodal receiver is made to provide the equalized digital output signal for the analog input signal.

Abstract: A memory cell includes a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node; a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell; and an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes; wherein the memory cell comprises a two gate pitch memory cell.

Abstract: A semiconductor device with a stacked power converter is described. In some examples, a semiconductor device includes: a first integrated circuit (IC) die having bond pads and solder bumps, the bond pads configured for wire-bonding; and a second IC die mounted on the first IC die, the second IC die having an active side and a backside opposite the active side, the second IC die including bond pads on the active side configured for wire-bonding, and solder bumps disposed on a backside opposite the active side; where the solder bumps of the first IC die are electrically and mechanically coupled to the solder bumps of the second IC die to form bump bonds.

Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract: An apparatus relates generally to multi-path digital predistortion. In this apparatus, a single-band digital predistorter engine has first and second sample paths. An input stage is coupled to receive input samples and configured to separate them into first samples and second samples. The input stage provides first and second magnitudes for the first and second samples, respectively. A first set of digital predistorters receives the first samples, the first magnitudes and the second magnitudes. A second set of digital predistorters receives the second samples, the second magnitudes and the first magnitudes. An output stage is coupled to receive predistorted outputs from the first set of digital predistorters and the second set of digital predistorters and is configured to provide a digital predistorted composite signal from the first set of digital predistorters and the second set of digital predistorters.

Abstract: A method relating generally to loading a boot image is disclosed. In such a method, a header of a boot image file is read by boot code executed by a system-on-chip. It is determined whether the header read has an authentication certificate. If the header has the authentication certificate, authenticity of the header is verified with the first authentication certificate. It is determined whether the header is encrypted. If the header is encrypted, the header is decrypted.

Abstract: An apparatus is disclosed for communication of data signals in a current-encoded format. The apparatus includes a first logic block and a second logic block. The first logic block includes a first voltage-mode logic (VML) circuit configured to provide a first voltage-encoded binary signal and an encoder circuit configured to convert the voltage-encoded binary signal to a current-encoded binary signal. The second logic block includes a decoder circuit configured to receive the current-encoded binary signal from the first logic block and convert the current-encoded binary signal to a second voltage-encoded binary signal. The logic states encoded by the second voltage-encoded binary signal are equal to the logic states encoded by the first voltage-encoded binary signal. The second logic block also includes a second VML circuit coupled to the decoder circuit and configured to receive and process the second voltage-encoded binary signal.

Abstract: A method, non-transitory computer readable medium and apparatus for correcting a timestamp in a multi-lane communication link with a skew are disclosed. For example, the method receives a data packet, a time stamp for the data packet and a fill level for a lane of the multi-lane communication link carrying the data packet, calculates a corrected timestamp for the data packet and replaces the time stamp for the data packet with the corrected timestamp.

Abstract: An apparatus for peak detection includes a peak identification unit configured to determine an identifier of a peak location; a first differential filter configured to provide coefficients for a first polynomial; a fractional locater configured to determine a fractional location of a peak based on the coefficients for the first polynomial and the identifier of the peak location; and a first fractional interpolator to determine a first peak amplitude based on the fractional location of the peak and the coefficients for the first polynomial.

Abstract: An integrated circuit device having memory is disclosed. The integrated circuit device comprises programmable resources; programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling a communication of signals with the programmable resources; a plurality of memory blocks; and dedicated interconnect elements coupled to the plurality of memory blocks, the dedicated interconnect elements enabling access to the plurality of memory blocks. A method of implementing memory in an integrated circuit device is also disclosed.

Abstract: A method relating generally to generating a boot image, as performed by an information handling system, for an embedded device is disclosed. This method includes a public key obtained by a boot image generator. A first hash for the public key is generated by the boot image generator. The first hash is provided to a signature generator. A first signature for the first hash is generated by the signature generator. A first partition for the boot image is obtained by the boot image generator. A second hash for the first partition is generated by the boot image generator. The second hash is provided to the signature generator. A second signature for the second hash is generated by the signature generator. The boot image generator and the signature generator are programmed into the information handling system. The boot image includes the public key, the first signature, and the second signature. The boot image is output from the information handling system.

Abstract: Embodiments of the invention generally provide an electronic device comprising an electrical interconnect component that includes an electrical trace. The electrical trace has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace have a thickness that is less than the skin depth, the current flows through substantially the entire cross-sectional area of the electrical trace for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.

Abstract: Approaches for estimating power consumption of an electronic circuit from values of configuration parameters. A user is prompted for values of a first subset of the configuration parameters in a first user interface window that is separate from a second user interface window that provides default values of a second subset of the configuration parameters. An estimated level of power consumption of the electronic circuit is determined by a computer as a function of the user-entered values of the first subset of parameters and the default values of the second subset of parameters. The estimated level of power consumption, the user-entered values of the first subset of parameters, and the default values of the second subset of parameters are simultaneously displayed in a third user interface window. The values of both the first subset and second subset of parameters are editable in the third user interface window.

Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.

Abstract: Implementations described herein generally relate to chip packaging, and in particular, to solder bump structures for a semiconductor device and methods of fabricating the same. In one implementation, a solder bump assembly is provided. The solder bump assembly comprises a conductive bond pad formed on a substrate. A conductive pillar is formed on the conductive bond pad. A plating layer is formed on the conductive pillar, wherein the plating layer comprises copper and nickel. A solder bump is formed on the plating layer in electrical communication with the plating layer. The plating layer may be a bi-layer structure comprising a nickel layer formed on the conductive pillar and a copper layer formed on the nickel layer in electrical communication with the solder bump. The plating layer may be a copper-nickel alloy.

Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.