Abstract: An apparatus relating generally to signal analysis is disclosed. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof, such as a start port for example, to receive a first output from the first comparator and coupled at a second port thereof, such as a stop port for example, to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.

Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.

Abstract: An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract: A method relates generally to channel equalization. In this method, a filter matrix is determined for transmission antennas by a channel equalizer of a first receiver processing chain. A first QR decomposition is performed on a first extended matrix for a first iteration. LLRs are fed from a second receiver processing chain to the first receiver processing chain for a second iteration. Symbol information is obtained from the LLRs. Interference is canceled using the symbol information to provide residual information. The channel equalizer is updated with the symbol information. The residual information is provided to the channel equalizer. User matrices corresponding to the transmission antennas are determined by the channel equalizer. This determination includes performing a second QR decomposition on a second extended matrix to obtain updated values for the user matrices, and performing updates using the symbol information and the updated values to provide the user matrices.

Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.

Abstract: An apparatus relates generally to a clock generator is disclosed. The clock generator is coupled to receive an input clock signal and further coupled to provide an output clock signal. An address and control register is coupled to receive an address signal and the output clock signal. An access generator is coupled to receive the output clock signal. The clock generator includes: an input node coupled to receive the input clock signal; at least one pulse generator coupled to the input node to receive the input clock signal and further coupled to provide a clock control signal; and a control gate coupled to the input node to receive the input signal and further coupled to the at least one pulse generator to receive the clock control signal. The clock control signal is provided in a non-toggling state for a high-frequency mode and in a toggling state for a low-frequency mode.

Abstract: A method of generating a digital image is described. The method comprises detecting light from a scene to form an image; identifying an aberration in the image; and implementing a color filter array interpolator based upon the detected aberration in the image. A device for generating a digital image is also described.

Abstract: In the disclosed methods, integrated circuit (IC) dice are manufactured from a common specification, and the IC dice are tested for defective circuitry. Respective defect sets are generated to indicate defective circuitry in the IC die. The dice are assigned to bins based on the respective defect sets. For each bin, all IC dice assigned to the bin have equivalent respective defect sets. Product definitions are provided, and each product definition indicates a respective set of circuitry required for a corresponding product. Respective sets of packages are manufactured for each product. In the manufacturing of each package of a respective set of packages for each product, one or more IC dice are selected from a subset of the plurality of bins such that the IC dice have respective defect sets allowed by the product definition of the product. The selected IC dice are then manufactured into the package.

Abstract: A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Abstract: An electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp, one or more first forward-biased diodes coupled in series between a supply node and the first node; and one or more second forward-biased diodes coupled in series between the first node and the third node. The RC-triggered clamp includes: an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node; a transistor with a first source/drain, a gate, and a second source/drain; and an inverter. The first source/drain of the transistor is coupled to the first node, and the second source/drain is coupled to the third node. An input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor.

Abstract: A method of performing digital pre-distortion in a communication network is described. The method comprises implementing a transceiver in the communication network, the transceiver enabling the transfer of communication signals in the communication network by way of a wireless communication channel; sampling signals, at the transceiver, associated with a transmit signal which are necessary to perform digital pre-distortion; providing the sampled signals to a remote computer; and generating, at the remote computer, parameters to be applied to a digital pre-distortion circuit of the transceiver. A communication network configured to enable digital pre-distortion is also described.

Abstract: An apparatus relates generally to crest factor reduction. In this apparatus, a finite impulse response filter provides a first cancellation pulse and a second cancellation pulse. A first adder is coupled to receive an input signal and the first cancellation pulse to provide a first difference signal. A peak engine is coupled to receive the first difference signal to provide a cancellation pulse value responsive to the first difference signal. The finite impulse response filter is coupled to receive the cancellation pulse value to provide each of the first cancellation pulse and the second cancellation pulse. A delay is coupled to receive the input signal to provide a delayed input signal. A second adder is coupled to receive the delayed input signal and the second cancellation pulse to provide a second difference signal. The second difference signal is a crest factor reduced version of the delayed input signal.

Abstract: A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described.

Abstract: Methods, computer-readable media and devices for executing a plurality of startup instructions are disclosed. For example, a method includes a first processor of a device accessing a plurality of startup instructions in response to a startup of the device. The first processor then executes a first startup instruction of the plurality of startup instructions to perform a first task and executes a second startup instruction of the plurality of startup instructions. The executing the second startup instruction causes the first processor to send a further instruction to a second processor of the device to perform a second task. At least a portion of the first task and at least a portion of the second task are performed at a same time.

Abstract: A decoding circuit is disclosed that includes a decoding pipeline configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding. The data block also includes a first and second sets of FEC datagrams for correcting received words of the plurality of data symbols encoded with the RS FEC coding and second FEC coding, respectively. Each decoding stage of the pipeline is configured to decode the plurality of data symbols using the first and second sets of FEC datagrams. A post-processing circuit connected to an output of the pipelines is configured to perform bitwise RS decoding of ones of the plurality of data symbols in error.

Abstract: An apparatus relating generally to voltage conversion includes an amplifier coupled to receive an input voltage and a reference voltage. First and second converters are coupled to the amplifier to receive a bias voltage. The first converter includes a first transconductor coupled to receive the bias voltage to adjust a first tail current, and a first differential input. A first inverter of the first converter has a first feedback device coupled input-to-output to provide a first transimpedance amplifier load. The first inverter is coupled to the first transconductor. The second converter includes a second transconductor coupled to receive the bias voltage to adjust a second tail current, and a second differential input. A second inverter of the second converter has a second feedback device coupled input-to-output to provide a second transimpedance amplifier load. The second inverter is coupled to the second transconductor.

Abstract: An apparatus relates generally to a repeater. In such an apparatus, the repeater has a signal analysis and classification block. The signal analysis and classification block includes a signal analysis block and a classification block. The signal analysis block is coupled to receive a digital signal which is a digital version of an input signal received by the repeater. The signal analysis block is coupled to provide signal information regarding the digital signal to the classification block. The classification block is configured to provide classification information to classify the digital signal using the signal information provided as being a waveform type of a group of waveform types.

Abstract: An apparatus relates generally to OFDM. In this apparatus, modulators are coupled to receive data inputs. Each of the modulators includes IDFT blocks coupled to output a first and a second N-point transform, and a 2N-point transform to provide discrete time domain signals for the data inputs. A switch and frequency translation block is coupled to receive the discrete time domain signals. RF ports are coupled to the switch and frequency translation block. The switch and frequency translation block is configured to allocate a combination of outputs from two or more of the IDFT blocks to a same RF port of the RF ports and to translate frequency of at least one of the outputs from the two or more of the IDFT blocks to provide the OFDM of the outputs from the two or more of the IDFT blocks onto the same RF port of the RF ports.

Abstract: An integrated circuit includes a stacked conductive layer interposer and a first die at least partially encapsulated in a mold material. The first die is mechanically and electrically attached to a top surface of the stacked conductive layer interposer using solder bumps. The integrated circuit further includes a first warpage correction layer.