Abstract: A dual latch character pacing circuit on a semiconductor chip controls data transfer between a pair of microprocessor which have significantly different data transfer rates. A first and second latch are connected in a parallel data path between the two microprocessor. The timing circuit includes a flip-flop which clocks the data between the latches. A one-shot timer is re-started on each transfer of data thereby insuring that the rate of transfer is substantially constant over a character period.

Abstract: In a light phase grating device, by forming the beam with a bottom conductive layer, the beam will not stick to the conductive layer on the substrate. The triboelectric effect will not occur, because the bottom conductive layer of the beam will allow charges to dissipate.

Abstract: A polysilicon resistor is added between a source (ground or power) of an EMI core circuitry and a source of the EMI peripheral circuitry. In this way, the electromagnetic interference of an integrated circuit is reduced. The added polysilicon resistor reduces the di/dt of the current passing between the power and the ground of the EMI core circuitry so that the EMI is reduced.

Abstract: Storing a variety of appliance control codes in a cordless digital telephone handset has the advantage that the cordless digital telephone handset can be used as a universal remote for a variety of electrical appliances. The cordless digital telephone handset need not be in the direct "line-of-sight" of the appliances in order to work. The appliance control data can be sent along with voice data in a method such as digital spread spectrum communications.

Abstract: An ICE system for emulating a device includes an EPROM storing control code, at least one RAM storing user code and data, a processor alternatively executing the control code and user code, and memory map switch logic dynamically switching the memory address map of the processor between monitor and user state configurations so as to minimally impact the target environment by maximizing the available memory address space for the user code and data when the processor is executing the user code.

Abstract: The present invention of a low voltage charge pump circuitry divides a charge pump circuitry into separate subsections. Each of the separate subsections is composed of a plurality of diode pump units connected in series. In addition, each of the separate subsections has its own pumper clock having different high voltage level and different frequency. A novel clock level shifter circuit is designed to provide the subsequent subsection a clock signal having the elevated high voltage level.

Abstract: A method and apparatus for addressing and writing data to extended I/O ports and additional RAM memory is provided, wherein a microprocessor sends both address and data information by way of a bus. The technique comprises the steps of writing to a first field of the bus an I/O port or RAM memory access code, to a second field of the bus an address for addressing a selected I/O port or RAM memory space for writing data thereto, and to a third field of the bus data which is to be written to the selected I/O port or RAM memory space; detecting whether the first field of the bus contains such access codes; decoding the address in the second field of the bus for selecting the selected I/O port; and writing data in third field of the bus to the selected I/O port or RAM memory if the access code has been detected.

Abstract: A flexible interrupt system for presenting interrupt signal to a microcontroller located on an integrated circuit responds to either on chip or off chip components. An interrupt circuit is connected to each bonding pad and is also connected to interrupt control logic which establishes priority for interrupt signals from the components located on chip. All interrupt signals pass through a common node in the interrupt circuit. A p channel transistor and a n channel transistor connected to the common node function as a pull up or pull down so that the microcontroller senses the rising or falling edge of the interrupt request. Since the interrupt request signals from either on chip components or off chip components pass through the common node, and the common node is directly coupled to a pad, system development and debug is simplified.

Abstract: A hot reconfigurable parallel bus bridging circuit is provided in a computer system which enables the computer system to communicate, via a peripheral port, with any one of plurality of incompatible standardized parallel bus systems. The hot reconfigurability of the bridging circuit of the present invention is accomplished using software to reconfigure or reprogram the various combinational logic gates, wait-state generators, and registers of the bridging circuit while the computer system is operating, without removing the bridging circuit from the computer system. The flexible hardware architecture of the present invention allows the computer system which houses this hardware to communicate with virtually any type of parallel bus system.

Abstract: A digital amplitude and phase detector for detecting the amplitude and phase of a color burst digital signal used in television systems is provided. The detector comprises a phase lock loop circuit for detecting the phase of said color burst signal and for generating a synchronous constant amplitude sinusoidal signal; multiplying circuit for generating a product signal by multiplying the color burst signal by the constant amplitude sinusoidal signal, wherein said product signal has a high-frequency component and a low-frequency component having an amplitude substantially proportional to that of the color burst signal; and low pass filter circuit coupled to said multiplying circuit for filtering said product signal such that the high-frequency component is substantially suppressed relative to that of the low-frequency component. A video encoder using the digital amplitude and phase detector is also provided.

Abstract: The technique takes advantage of the current ability to increase the density of electronic circuit elements on an integrated circuit chip by combining onto a single chip all of the circuit elements of two or more separate circuits, even when the masks of the separate circuits have been laid out with one or more different design rules, and then connect them to operate together. A mask layout database of one of the circuits at a time is globally changed, with the use of a standard computer software package, to conform it to the design rules of the mask layout database of another circuit, either before or after the circuit databases are combined into a single database.

Abstract: A dynamic power management device for supplying power to a solid state memory integrated circuit includes power control circuitry for supplying a variable voltage to the memory integrated circuit and logic control circuitry responsive to data access activity for generating address and control signals for the memory integrated circuit and for controlling the power control circuitry to supply power to the memory integrated circuit sufficient to maintain memory information in the memory integrated circuit during periods of no data access activity and sufficient to exchange memory information with the memory integrated circuit during periods of data access activity. Power consumption of the memory integrated circuit is thereby curtailed.

Abstract: A MOS precision capacitor is formed in an integrated circuit including a p-mos and n-mos transistor without adding to the process steps used in forming the p-mos and n-mos transistor. The MOS precision capacitor includes a n-well formed concurrently with a n-well of the p-mos transistor, a n-type region formed concurrently with a threshold adjust region of the p-mos transistor, an oxide layer formed concurrently with gate oxide layers of the p-mos and n-mos transistors, a first electrode formed over the n-type region, at least one n+ region formed concurrently with source and drain regions of the n-mos transistor by self aligning to the sidewall of the first electrode, and a second electrode connected to the at least one n+ region.

Abstract: A digital circuit is used to demodulate a linear chirp spread spectrum signal. The digital circuit uses a counter which is clocked so as to count during the time period between the pulses of a chirp signal. The circuitry also uses a digital filter to determine whether the frequencies of the linear chirp signal are within the correct bandwidth. The output of the counter is compared with the previous count to produce a difference count. A processor uses this difference count value to determine the characteristics of a chirp signal being decoded. A difference signal test circuit provides a digital filter for the difference count to eliminate spurious noise conditions.

Abstract: In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions they are fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.

Abstract: A time multiplexing technique and corresponding circuitry is described which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer's inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.

Abstract: The present invention involves adding additional structures to a polysilicon resistor which do not significantly affect the resistance of the polysilicon resistor. These additional structures add to the area of the polysilicon resistor, and therefore reduce the self-induced temperature change caused by the voltage across the resistor. Since the resistance of the polysilicon resistor depends on its temperature, the reduction of the self-induced temperature change lowers the variation in the resistance value at different voltages.

Abstract: A method of forming ROM transistor memory cell including not forming lightly doped regions in the semiconductor substrate for some of the memory cells so as to form one type of memory cell and forming the lightly doped regions in another type of memory cell.

Abstract: A device for automatic transfer of status information concerning data blocks between a microprocessor controlled system and a peripheral device where a direct memory access controller (DMA) is used for transferring data. The status information concerning a certain data block is stored in status registers where the status information is received from either the microprocessor controlled system or the peripheral device. The DMA controls the transfer of data between the two systems where the blocks of data are stored in a FIFO. Each data block contains at its end an end of data indicator. A state machine and counter responds to the end of data indicator of a data block upon the completion of the transfer of the data block to generate an enabling signal for transferring the status information from the register as if it were part of the data block. This is performed in a manner transparent to the DMA and the microprocessor to obviate the need of microprocessor intervention.

Abstract: Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.