Abstract: A Method and System for Preventing Bum-out of Infrared Transmitter Diodes is disclosed. The preferred method and system detects when the Ir transmitter(s) are approaching or have achieved an overtemperature condition. Once an overtemperature condition is detected, the preferred system will interrupt electrical transmit power to the transmitter until such time as the overtemperature condition is dissipated. Furthermore, the system and method will send a standby signal to the Central Processing Unit or communications controller when an overtemperature condition is detected. Finally, it is yet another feature that the system emit status signals perceptible to the human senses when normal and abnormal temperature conditions are detected in the transmitter.

Abstract: A CMOS switch circuit includes a first stage having PMOS and NMOS transistors arranged and properly sized to provide substantially concurrently switching complementary outputs, and a second stage having PMOS and NMOS transistors arranged and related to counterparts in the first stage so as to provide substantially concurrently switching complementary outputs that are substantially process independent.

Abstract: A high voltage level shifter includes one or more complementary pairs of transistors connected together in series separate the output terminal from the input terminal so as to prevent junction breakdowns, oxide breakdowns, and punch-through breakdowns.

Abstract: A circuit for detecting and selecting one of clock signals of at least two clock sources, is provided. The circuit is coupled to the available clock sources so as to receive their clock signals. The circuit is programmable to choose one of the clock signals designated by a programmed code. Then, the circuit [1] selects the designated clock signal when it has been received and [2] automatically selects the undesignated clock signal when the designated clock signal has not been received and when the undesignated clock signal has been received. Thereafter, the circuit provides the selected clock signal to any device that requires a clock signal in order to operate.

Abstract: An Improved Optics System for Infrared Signal Transceivers is disclosed. Transceivers. The preferred system includes an IR transceiver assembly that is easily grasped by assemblers. Furthermore, the primary and secondary lenses associated with the transceiver system are easier to manufacture than current lens designs. Also, the heretofore critical lens separation between the emitter/detector devices and the primary lens is rendered a flexible dimension, dependent only upon the particular appliance in which the system is installed. The present invention permits the stand for emitter/detector devices to be eliminated as a result of exchanging a non-imaging transceiver system with the current imaging transceiver system. Finally, the present invention comprises assembling or otherwise combining emitter/detector devices into a single emitter/detector device stack.

Abstract: An amplifier circuit with small die size and low power consumption is described. The design allows a number of switch amplifier circuits to be placed on a single chip. Each of the amplifiers contains a comparator for greater amplification, with a designed-in offset, a small pull-down current, and a diode. The comparators are biased with low current values and the need for large resistors is eliminated. Several such devices can be placed on a chip along with an edge triggered shift register to store the logic levels generated from the switch inputs. The offset, either built-in or externally supplied, sets one comparator input to an offset voltage. The switch is connected to the other input, with the diode and pull-down in parallel between this input and ground or other reference level: When the switch is open, the pull-down takes the input to ground; when the switch is closed, the diode voltage drop holds the input to a voltage above the offset.

Abstract: A method and circuits, in a non-volatile memory system such as EPROM, for limiting bit line current during programming that includes biasing a driving transistor to mirror a maximum desired current into the driving transistor from a mirroring transistor connected to a controlled current source. This technique is useful, for example, during hot electron programming of a floating gate memory cell to limit bit line current caused by snap back of the cell through which a relatively high current is passed. In a preferred embodiment, the state of a cell is monitored while being programmed by comparing the voltage of the bit line with a reference voltage that is developed in a circuit containing a replica of the driving transistor.

Abstract: The present invention provides a method of forming a high quality thin oxide on a semiconductor body. A sacrificial oxide is formed on the semiconductor and then etched to eliminate the surface contamination of the semiconductor body. Then, an EEPROM oxide is formed following by an arsenic implant. Next the EEPROM oxide on the semiconductor body is then prepared by thin oxide growth. The thin oxide is preferably formed in a steam ambient. Subsequently, the oxide is annealed under nitrous oxide ambient using a combination of in-situ and RTP annealing process.

Abstract: A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the time durations of the output clock of a voltage-controlled oscillator with the system clock for N cycles. A correction signal is then generated by comparing these two time durations, and the correction signal is fed back to the voltage-controlled oscillator to eliminate the difference in the time durations. In addition, the voltage-controlled oscillator is also synchronized with the synchronizing signal by using the synchronizing signal as a reset.

Abstract: The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.

Abstract: Deposited dielectric layers for a semiconductor device are typically formed in a chemical vapor deposition. Often a hydrogen by-product is formed. Especially in a plasma enhanced chemical vapor deposition process, the hydrogen by-product can form free radicals that are introduced into the dielectric layers. The hydrogen free radicals can affect the stability of the threshold and breakdown voltage of MOSFET transistors. Deuterium introduced into the CVD chamber competes to enter the dielectric layer with the hydrogen. The deuterium prevents some of the hydrogen free radicals from entering the dielectric layer and thus increases MOSFET reliability.

Abstract: An improved DMA controller is provided. The improved DMA controller uses a peripheral control bus which has scan codes to indicate the DMA channel, conventional data request/data acknowledge lines, and additional lines indicating a "terminate," "type fetch," "end of buffer" and "store status." List entries are associated with the buffers in the memory. Each list entry has a type/status field which can be coded with information indicating "ready buffer," whether to notify "end of buffer," "buffer in progress," "completed buffer without status," "completed buffer with status," "ready buffer with command," and "ready buffer without command." The type of status byte can be checked before processing the buffers.

Abstract: An apparatus having a power supply terminal, a capacitor terminal, and a load terminal for distributing power from the power supply terminal to the capacitor terminal. The apparatus has a driver which supplies load current to the load terminal in response to a control signal, a controller which generates the control signal, and is coupled to the capacitor terminal, and a switching device. The switching device couples the power supply terminal to the controller and the capacitor terminal when the driver does not supply the load current to the load terminal, and decouples the power supply terminal from the controller and the capacitor terminal when the driver supplies the load current to the load terminal. As a result, the controller is effectively isolated from the noisy power supply.

Abstract: A method for use with digital automated test equipment for measuring an asynchronous analog frequency, which analog frequency may be up to at least four times the operational frequency of the digital automated test equipment. From test vectors related to the frequency of interest known to represent good components, a pattern of test vectors with randomly assigned timing sets is created. Then, the maximum number of counts and the period increment is set. The selected pattern of test vectors are then applied to the unit under test and the received waveforms compared to the stored patterns. If there is no match, the period of the timing sets within the frequency range of interest is adjusted by a predetermined increment, and the test is repeated until there is a match. Since the period is now known, the frequency of the asynchronous analog signal can be calculated.

Abstract: A method for generating a video character in an on-screen display system. The method uses a HALT signal provided to the microprocessor which allows the microprocessor to finish executing its current instruction, but prohibits the microprocessor from beginning a next instruction. After a sufficient amount of time has passed to ensure that the microprocessor has completed its current instruction, an OSD interrupt signal is sent to the microprocessor instructing the microprocessor to begin OSD operations. Alternatively, the method uses a bus multiplexer which duplicates character data and sends the expanded data to a bus in order to enlarge characters displayed on the screen.

Abstract: An apparatus and method for synchronizing and tracking an input data stream and for generating a synchronous clock therefrom, comprising means for generating a plurality of clock signals oscillating at substantially the same frequency, but with different phases; a plurality of delay lines having a common data input for receiving said input data stream, each delay line having multiple delay elements connected in series and having a common clock input for receiving one of said clock signals for clocking data of said data stream along said delay line in a direction away from said common data input; means for detecting which of said plurality of delay lines said data from said data stream is propagating therein; and means for generating the synchronous clock based on one of said clock signals that clocks the delay line that data from said data stream is propagating therein.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: A phase locked loop is described which uses a first and second voltage-controlled oscillator. The first voltage-controlled oscillator is input into a feedback circuit which is used to produce a control signal. The control signal runs both the first and second voltage-controlled oscillators. A synchronization circuit is used to synchronize the first voltage-controlled oscillator with the synchronization pulse. In one embodiment, the synchronization circuit can use the second voltage-controlled oscillator to produce a timing interval to control the turning on and off of the second voltage-controlled oscillator in order to facilitate this synchronization. Because the output of the first voltage-controlled oscillator is sent to the feedback, the output of the phase locked loop will not drift due to parameter differences between the first and second voltage-controlled oscillators.

Abstract: A reconfigurable infinite impulse response low-pass filter is described in which the frequency response can be changed by changing a single parameter while the filter gain of the filter remains constant, preferably, unity. The parameter value is used to calculate the coefficients for the infinite impulse response filter. By choosing the parameter values carefully, the infinite impulse response filter can be implemented using shift registers rather than multipliers to reduce the hardware complexity of the infinite impulse response filter.

Abstract: By forming a digital video processor and digital television controller on the same integrated circuit, a number of advantages in improved picture quality can be obtained. The length of the communication connections between these two elements can be reduced, thus reducing television picture distortion caused by electromagnetic interference. Additionally, the elements can be controlled by a single dot clock generator with a single phase locked loop circuit. Also, register banks can be used for intercommunication between the television controller and the video processor rather than the communication between two different ICs over a bus.