Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 10324852
    Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Theodros Yigzaw, Ashok Raj, Robert C. Swanson, Mohan J. Kumar
  • Patent number: 10324519
    Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Yoni Aizik, Doron Rajwan, Gal Leibovich, Nadav Shulman, Hisham Abu Salah
  • Patent number: 10324862
    Abstract: Implementations of the disclosure provide for supporting oversubscription of guest enclave memory pages. In one implementation, a processing device comprising a memory controller unit to access a secure enclave and a processor core, operatively coupled to the memory controller unit. The processing device is to identify a target memory page in memory. The target memory page is associated with a secure enclave of a virtual machine (VM). A data structure comprising context information corresponding to the target memory page is received. A state of the target memory page is determined based on the received data structure. The state indicating whether the target memory page is associated with at least one of: a child memory page or a parent memory page of the VM. Thereupon, an instruction to evict the target memory page from the secure enclave is generated based on the determined state.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Gilbert Neiger, Asit K. Mallick, Ittai Anati, Ilya Alexandrovich, Vedvyas Shanbhogue, Somnath Chakrabarti
  • Patent number: 10322203
    Abstract: An apparatus for air flow generation for scent output is described. The device includes a scent system, a speaker, and an output channel. The scent system and the speaker share the output channel, and the speaker is to move air to release scent from the device. A membrane of the speaker may vibrate to produce the air flow.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Mikko Kursula, Seppo Vesamaki, Matti A. Lahdenpera, Timo H. Nissinen, Marko Vaaranmaa
  • Patent number: 10324863
    Abstract: Generally, this disclosure provides systems, methods and computer readable media for a protected memory view in a virtual machine (VM) environment enabling nested page table access by trusted guest software outside of VMX root mode. The system may include an editor module configured to provide access to a nested page table structure, by operating system (OS) kernel components and by user space applications within a guest of the VM, wherein the nested page table structure is associated with one of the protected memory views. The system may also include a page handling processor configured to secure that access by maintaining security information in the nested page table structure.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Michael Lemay, David M. Durham, Ravi L. Sahita, Andrew V. Anderson
  • Patent number: 10324525
    Abstract: Context aware backlighting techniques include determining a focal point of a display space based on a user display context. The user display context represents an area of interest on the monitor. The user display context can be based on eye tracking data, ambient light data, motion sensing data, cursor location in the display space, an image content, proximity data, or the like and any combination thereof. A first set of one or more of a plurality of backlight sections corresponding to the determined focal point of the display space can be driven to output at a first intensity level, while a second set of one or more of the plurality of backlight sections can be driven to output at a second intensity level.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Dhaval V. Sharma, Nivruti Rai, Durgesh Srivastava, Shobhit Kumar
  • Patent number: 10324494
    Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for detection of a change of electromagnetic field in response to a gesture, to identify the gesture that caused the field change. In one instance, the apparatus may include a first conducting component having first features for the disposal on or around a portion of a user's body, to generate an electromagnetic field in response to a receipt of a source signal. The apparatus may further include a second conducting component having second features for the disposal on or around a portion of the user's body, at a distance from the first conducting component, to provide an indication of a change in the electromagnetic field over time, to identify a change of a position of the user's body portion (gesture) that causes the change in the electromagnetic field. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Jose Rodrigo Camacho Perez, Carlos Alberto Lopez Perez, Paulo Lopez Meyer, Alejandro Ibarra Von Borstel, Julio Cesar Zamora Esquivel, Hector Alfonso Cordourier Maruri
  • Patent number: 10324857
    Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Joseph Nuzman, Raanan Sade, Igor Yanover, Ron Gabor, Amit Gradstein
  • Patent number: 10324124
    Abstract: A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Linda K. Sun, Harry Muljono
  • Patent number: 10325840
    Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Mark T. Bohr, Patrick Morrow
  • Patent number: 10325341
    Abstract: One embodiment provides for a general-purpose graphics processing unit comprising multiple processing units and a pipeline manager to distribute a thread group to the multiple processing units, wherein the pipeline manager is to distribute the thread group as multiple thread sub-groups.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Altug Koker, Joydeep Ray
  • Patent number: 10326590
    Abstract: Technologies for trusted device on-boarding include a first computing device to generate a first public Diffie-Hellman key based on a private Diffie-Hellman key and a first unique identifier of the first computing device. The first unique identifier is retrieved from secure memory of the first computing device. The first computing device transmits the first public Diffie-Hellman key to a second computing device and receives, from the second computing device, a second public Diffie-Hellman key of the second computing device. The second public Diffie-Hellman key incorporates a second unique identifier of the second computing device. Further, the first computing device removes a contribution of the second unique identifier from the second public Diffie-Hellman key to generate a modified public Diffie-Hellman key and generates a shared Diffie-Hellman key based on the modified public Diffie-Hellman key and the private Diffie-Hellman key of the first computing device.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Jesse Walker, Mats Agerstam, Ravi S. Subramaniam, Eduardo Cabre
  • Patent number: 10325665
    Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Richard Fastow, Xin Sun, Uday Chandrasekhar, Krishna K. Parat, Camila Jaramillo, Purval S. Sule, Aliasgar S. Madraswala
  • Patent number: 10326931
    Abstract: An apparatus and method are provided for viewing panoramic images and videos through the selection of a particular viewing angle and window (zoom) within that panorama while allowing the viewer to simultaneously implement temporal transport control, allowing the video to be in a state of pause, play, fast forward, fast rewind, slow forward, slow rewind, or frame-by-frame. This capability may be used on video that is residing in memory on the viewer's viewing system, in a hard disk local to the viewer or in a shared location, or on a live buffered feed of video. A second capability of this apparatus and method relates to the use of a plurality of panoramic video or images from multiple synchronized cameras. In those cases, all panoramic video feeds are synchronized so that as a viewer pauses, rewinds, forwards a video in one panorama, all panoramas are time synchronized and go through the same states as the panorama being viewed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Sankar Jayaram, Ritesh Kale, Charles DeChenne, John Harrison, Franklin W. Taylor, Vikas K. Singh
  • Patent number: 10327331
    Abstract: Some forms relate to a stretchable computing device. The stretchable computing device includes a first layer that includes electrical interconnects at a first density wherein the first layer includes a first electronic component; a stretchable second layer electrically connected to the first layer, wherein the stretchable second layer includes electrical interconnects at a second density that is less than the first density, wherein the second layer includes a second electronic component; and a stretchable third layer electrically connected to the stretchable second layer, wherein the stretchable third layer includes electrical interconnects at a third density that is less than the second density.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Nadine L. Dabby, Adel A. Elsherbini, Braxton Lathrop, Sasha N. Oster, Aleksandar Aleksov
  • Patent number: 10326711
    Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker, Steven F. Hoover, Gregory J. Hubbard
  • Patent number: 10325774
    Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Benjamin Chu-Kung, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 10326558
    Abstract: Some demonstrative embodiments include apparatus, system and method of communicating a Single Carrier (SC) transmission. For example, an apparatus of a SC Physical Layer (PHY) transmitter may include a spatial stream parser to distribute encoded bits of a Physical Layer Convergence Procedure (PLCP) Service Data Unit (PSDU) to a plurality of spatial streams; a plurality of constellation mappers to map encoded bits of the plurality of spatial streams into a respective plurality of streams of constellation symbols according to a constellation scheme; a Space Time Block Code (STBC) encoder to encode the plurality of streams of constellation symbols into SC symbol blocks over a plurality of space-time streams; and a transmit beamforming module to map the plurality of space-time streams to a plurality of transmit chains.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Artyom Lomayev, Iaroslav P. Gagiev, Alexander Maltsev, Michael Genossar, Carlos Cordeiro
  • Patent number: 10325708
    Abstract: A Near Field Communications (NFC) antenna coil, having a first loop; and a second loop connected to the first loop to form a spiral shape, wherein the first loop and the second loop have different sizes to be mutually couplable with a first antenna pairing coil and a second antenna pairing coil, respectively.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang
  • Patent number: 10327216
    Abstract: Methods and devices for performing a page synchronization of a communication signal having a page structure with at least one repeating feature, the methods and devices configured to demodulate the communication signal to produce a raw symbol stream; correlate a plurality of subsets of the raw symbol stream with a page synchronization pattern; detect which of the plurality of subsets meet a pre-determined correlation condition; and identify two of the detected subsets based on a characteristic of the at least one repeating feature.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 18, 2019
    Assignee: INTEL IP CORPORATION
    Inventor: Vinay Simha
  • Patent number: 10325860
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Patent number: 10326596
    Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Vikram Suresh, Sudhir Satpathy, Sanu Mathew
  • Patent number: 10325866
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Eric Li, Joshua Heppner, Rajendra Dias, Mitul Modi
  • Patent number: 10327143
    Abstract: Some demonstrative embodiments include devices, systems and/or methods of communicating between a cellular manager and a User Equipment (UE) via a Wireless Local Area network (WLAN) node. For example, an Evolved Node B (eNB) may be configured to communicate with a User Equipment (UE) traffic of at least one Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) Radio Access Bearer (E-RAB); to participate in establishment of an IP tunnel with the UE via a Wireless Local Area Network (WLAN) node; to encapsulate an IP payload comprising downlink traffic of the E-RAB in an IP tunneling packet; and to send the IP tunneling packet to the UE via the IP tunnel.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: June 18, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Alexander Sirotkin, Nageen Himayat, Farid Adrangi
  • Patent number: 10326075
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Patent number: 10327200
    Abstract: A communication manager of a communication network can include a transceiver configured to communicate with communication stations and one or more clients of the communication network, and a controller. The controller can be configured to: generate a management packet and provide, using the transceiver, the management packet to the communication stations to control the communication stations to monitor a communication from the client of the one or more clients and measure the client communication; obtain respective measurements from the communication stations using the transceiver; and control the client of the one or more clients to select a communication station from the communication stations to serve the client based on the respective measurements.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Segev Ravgad, Roni Abiri
  • Patent number: 10325652
    Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
  • Patent number: 10325861
    Abstract: Dicing a semiconductor wafer into chips may include (and structures may result from) forming a lateral chip dicing pattern of vertical metal stack kerf (MSK) structures from a depth below an upper surface of a substrate of a wafer, up through metallization layers of the wafer, to a top surface of the wafer. This dicing pattern may separate or define the perimeters/edges of the chips to be diced. A protective layer over the wafer can be etched to form a pattern of openings to the pattern of MSK structures. Then, a wet etch through the pattern of openings in the protective layer removes the MSK structures and forms lateral chip dicing trench pattern to the depth below the upper surface of the substrate along the intended lateral dicing pattern. A bottom surface of the substrate can be ground to expose the bottom of the trench pattern and dice the chips.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventor: Giuseppe Miccoli
  • Patent number: 10326211
    Abstract: Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Adel Elsherbini
  • Patent number: 10327233
    Abstract: Techniques are described for compressing the PUCCH resources reserved for acknowledging downlink data transmissions when those resources are implicitly signaled by EPDCCHs that schedule the downlink transmissions in TDD mode. An acknowledgement resource offset field transmitted in the EPDCCH is configured to correspond to one or more values that compress the region in PUCCH resource index space that would otherwise be reserved for the subframes of a bundling window.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Seunghee Han, Yuan Zhu, Xiaogang Chen, Jong-Kae Fwu
  • Patent number: 10326575
    Abstract: Methods, systems, and storage media for providing multi-cell, multi-point single user (SU) multiple input and multiple output (MIMO) operations are described. In embodiments, an apparatus may receive and process a first set of one or more independent data streams received in a downlink channel from a first transmission point. The apparatus may receive and process a second set of one or more independent data streams received in a downlink channel from a second transmission point. The apparatus may process control information received from the first transmission point or the second transmission point. The control information may include an indication of a quasi co-location assumption to be used for estimating channel characteristics for reception of the first set of one or more independent data streams or the second set of one or more independent data streams. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Alexei Davydov, Gregory Morozov, Vadim Sergeyev, Alexander Maltsev, Ilya Bolotin
  • Patent number: 10326330
    Abstract: Methods, apparatus, systems and articles of manufacture to implement cooling fans with selectively activated vibration modes are disclosed. An example cooling fan assembly includes a motor and a fan coupled to a shaft of the motor. The motor is to rotate the shaft in a first direction to cause the fan to move air. The motor is to rotate the shaft in a second direction to cause vibration from an eccentric mass coupled to the shaft.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mikko Kursula, Kalle I. Makinen, Tapio Liusvaara
  • Patent number: 10327330
    Abstract: Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Javier Soto Gonzalez, Dilan Seneviratne, Shruti R. Jaywant, Sashi S. Kandanur, Srinivas Pietambaram, Nadine L. Dabby, Braxton Lathrop, Rajat Goyal, Vivek Raghunathan
  • Patent number: 10325344
    Abstract: A mechanism is described for facilitating dynamic merging of atomic operations in computing devices. A method of embodiments, as described herein, includes facilitating detecting atomic messages and a plurality of slot addresses. The method further includes comparing one or more slot addresses of the plurality of slot addresses with other slot addresses of the plurality of slot addresses to seek one or more matched slot addresses, where the one or more matched slot addresses are merged into one or more merged groups. The method may further include generating one or more merged atomic operations based on and corresponding to the one or more merged groups.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Altug Koker, Abhishek R. Appu, Balaji Vembu
  • Patent number: 10326293
    Abstract: An electronic device may include a battery charger and a controller. The battery charger may receive a voltage from an energy source, and may provide an output power. The controller may receive a voltage value of the energy source, may receive a current value from the battery charger or the energy source, may determine a power value based on the received voltage value and the received current value, and may provide at least one control signal to the battery charger to change the output power of the charger.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Lilly Huang, Wayne Proefrock, Krishnan Ravichandran, Alexander Uan-Zo-Li
  • Patent number: 10325382
    Abstract: A contextual image manipulation apparatus may include an image part identifier to identify a part of an image, an information collector to collect information from at least one external source, a context identifier communicatively coupled to the information collector to determine contextual information from the collected information and at least one other contextual source, and an image manipulator communicatively coupled to the image part identifier and the context identifier to alter a feature of the image part based on the contextual information.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Shahar Taite, Tomer Rider, Shay Pluderman
  • Patent number: 10327163
    Abstract: Embodiments of a UE and methods for D2D communication are generally described herein. The UE may transmit, as part of an in-network communication session, a D2D discovery status message. The D2D discovery status message may indicate an initiation or termination of a D2D discovery operation at the UE and may indicate if the UE is announcing or monitoring as part of the D2D discovery operation. The D2D discovery operation may be at least partly for configuring a D2D communication session between the UE and one or more other UEs. The UE may transmit, as part of the D2D discovery operation, a D2D discovery signal for reception at one or more other UEs. The UE may transmit and receive D2D packets over a direct link to a second UE as part of the D2D communication session.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Youn Hyoung Heo, Pingping Zong, Alexandre Saso Stojanovski, Achim Luft
  • Patent number: 10325118
    Abstract: Memory security technologies are described. An example processing system includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can receive a content read instruction from an application. The processor core can identify a cache line (CL) from a plurality of CLs of a cryptographic cache block (CCB) requested in the content read instruction. The processor core can load, from a cryptographic tree, tree nodes with security metadata. The processor core can retrieve, from the memory, the CCB. The processor core can generate a second MAC from the CCB. The processor core can compare the first MAC with the second MAC. The processor core can decrypt the CCB using security metadata when the first MAC matches the second MAC. The processor core can send at least the identified CL from the decrypted CCB to the application.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Francis X. Mckeen, Carlos V. Rozas, Saeedeh Komijani, Tamara S. Lehman
  • Patent number: 10326514
    Abstract: Disclosed herein are apparatuses, systems, and methods for reference signal design for initial acquisition, by receiving a first primary synchronization signal (PSS) and a first secondary synchronization signal (SSS) from a first transmit (Tx) beam, in first contiguous orthogonal frequency division multiplexing (OFDM) symbols of a downlink subframe. A UE can receive at least a second PSS and a second SSS from a second Tx beam in contiguous OFDM symbols of the downlink subframe. A UE can then detect beamforming reference signals (BRSs) corresponding to the first Tx beam and the second Tx beam, based on identification of physical cell ID information and timing information processed from the first PSS, the second PSS, the first SSS, and the second SSS. The UE can select the first Tx beam or the second Tx beam that was received with the highest power, based on the BRSs. Other embodiments are described.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Gang Xiong, Huaning Niu, Yushu Zhang, Jong-Kae Fwu, Yuan Zhu, Ralf Matthias Bendlin
  • Patent number: 10325590
    Abstract: A language model is modified for a local speech recognition system using remote speech recognition sources. In one example, a speech utterance is received. The speech utterance is sent to at least one remote speech recognition system. Text results corresponding to the utterance are received from the remote speech recognition system. A local text result is generated using local vocabulary. The received text results and the generated text result are compared to determine words that are out of the local vocabulary and the local vocabulary is updated using the out of vocabulary words.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Michael Deisher, Georg Stemmer
  • Patent number: 10326587
    Abstract: A cryptography accelerator system includes a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and an on-the-fly hashing circuit to hash data read from a first memory circuit on-the-fly before writing the read data to a second memory circuit. The hashing circuit performs at least one of integrity protection and firmware/software (FW/SW) verification of the data prior to writing the data to the second memory circuit. The on-the-fly hashing circuit includes a bit repositioning circuit to designate an order of bits of a binary word in a register from a most significant bit (MSB) to a least significant bit (LSB) for performing computations without rotating bits in the register, and an on-the-fly round constant generator circuit to generate a round constant from a counter.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Li Zhao, Rafael Misoczki, Manoj R Sastry
  • Patent number: 10325814
    Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Swaminathan Sivakumar
  • Patent number: 10327268
    Abstract: A microelectronic package is described with a wireless interconnect for chip-to-chip communication. In one example, the package includes an integrated circuit chip, a package substrate to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components, a radio coupled to the integrated circuit chip to receive data from the integrated circuit chip and modulate the data onto a radio frequency carrier, and an antenna on the package substrate coupled to the radio to send the modulated data over the carrier to an external device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Adel A. Elsherbini, Emanuel Cohen
  • Patent number: 10325843
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Qinglei Zhang, Stefanie M. Lotz
  • Patent number: 10327209
    Abstract: The disclosure relates to a baseband processing method, comprising: receiving a downlink (DL) baseband (BB) signal in a transmission time interval (TTI), wherein the DL BB signal comprises a time-frequency resource comprising a control section and a data section; decoding at least part of the control section to detect a DL grant information; if the DL grant information is detected, determine a number of granted data resource blocks from the DL grant information; and adjust at least one of a clock rate and supply voltage of the baseband processing based on the number of granted resource blocks.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Zhibin Yu, Rajarajan Balraj
  • Patent number: 10327207
    Abstract: Embodiments are described herein for selective joinder of wireless cells by machine-type communication (“MTC”) user equipment (“UE”). An MTC UE may detect a plurality of wireless cells, each provided by an evolved Node B (“eNB”). The MTC UE may detect eNB categories associated with individual wireless cells of the plurality of wireless cells, and may identify one or more wireless cells of the plurality of detected wireless cells on which MTC traffic is permitted based on the associated eNB categories. The MTC UE may selectively join a wireless cell of the one or more identified wireless cells based on a cell selection criterion. Additionally, an eNB may provide a wireless cell and provide, to an MTC UE, an MTC policy that identifies a circumstance under which the eNB will permit MTC traffic. The eNB may be configured to selectively serve the MTC UE based on the MTC policy.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Puneet Jain, Sangeetha Bangolae, Marta Martinez Tarradell, Mo-Han Fong
  • Publication number: 20190182824
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus of a machine-type communication (MTC) user equipment (UE) comprises baseband processing circuitry to establish a radio resource control (RRC) connection with an evolved Node B (eNB), and process a message from the eNB indicating a number of repetitions of physical uplink control channel (PUCCH) transmissions to be used over multiple uplink subframes after the radio resource control connection is established.
    Type: Application
    Filed: March 31, 2016
    Publication date: June 13, 2019
    Applicant: Intel IP Corporation
    Inventor: Debdeep Chatterjee
  • Publication number: 20190182839
    Abstract: Techniques for opportunistic resource sharing between mobile devices are described. A method comprises identifying a set of homogeneous device resources implemented by multiple devices based in part on resource configuration information received by a wireless transceiver, selecting a shared homogeneous device resource of one of the multiple devices to share between the multiple devices, and sending shared configuration information to identify the shared homogeneous device resource and a share role for each of the multiple devices. Other embodiments are described and claimed.
    Type: Application
    Filed: February 15, 2019
    Publication date: June 13, 2019
    Applicant: INTEL CORPORATION
    Inventor: Kevin C. Wells
  • Publication number: 20190180038
    Abstract: Methods, articles, and systems of computer graphics processing system validation for processing of encrypted image content are disclosed herein.
    Type: Application
    Filed: February 16, 2019
    Publication date: June 13, 2019
    Applicant: Intel Corporation
    Inventors: Ashwin Muppalla, Changliang Wang, Penne Lee
  • Publication number: 20190181337
    Abstract: Disclosed herein are metal filament memory devices (MFMDs), and related devices and techniques. In some embodiments, an MFMD may include: an electrode including an electrochemically active metal; an electrolyte; and a barrier material disposed between the electrode and the electrolyte, wherein the barrier material has a lower work function than the electrode.
    Type: Application
    Filed: September 25, 2016
    Publication date: June 13, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Elijah V. Karpov, Roza Kotlyar, Prashant Majhi