Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 10310734
    Abstract: Tier access mode for three dimensional (3D) memory devices. A 3D memory device has multiple memory elements that are each addressable by a two dimensional address including a wordline address and a bitline address, and a third dimension with a sub-block selector indicating one of multiple portions of a tier of memory elements in the memory device. A memory controller generates a memory access command, such as read or program, to access a first portion of the memory and sends the command to the memory device. The memory device charges a first wordline and a first sub-block in response to receiving the command. For a consecutive access command to access a second portion of the memory, the memory device maintains the first wordline charged without discharging it, and charges a second sub-block selector in response to the consecutive command.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Toru Tanzawa
  • Patent number: 10311000
    Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Siang Lin Tan, Su Wei Lim, Ming Chew Lee, Ofer Nathan
  • Patent number: 10310974
    Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Cunming Liang, Edwin Verplank, David E. Cohen, Danny Zhou
  • Patent number: 10310826
    Abstract: Technologies for automatic reordering of sparse matrices include a computing device to determine a distributivity of an expression defined in a code region of a program code. The expression is determined to be distributive if semantics of the expression are unaffected by a reordering of an input/output of the expression. The computing device performs inter-dependent array analysis on the expression to determine one or more clusters of inter-dependent arrays of the expression, wherein each array of a cluster of the one or more clusters is inter-dependent on each other array of the cluster, and performs bi-directional data flow analysis on the code region by iterative backward and forward propagation of reorderable arrays through expressions in the code region based on the one or more clusters of the inter-dependent arrays. The backward propagation is based on a backward transfer function and the forward propagation is based on a forward transfer function.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Hongbo Rong, Jongsoo Park, Todd A. Anderson
  • Patent number: 10310987
    Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 4, 2019
    Assignee: INTEL CORPORATION
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Patent number: 10310832
    Abstract: System and techniques for an internet-of-things device blank are described herein. An IoT blank device may be tested to determine whether it is in an initial state. In response to a determination that the IoT blank device is in the initial state, a cloud endpoint may be contacted, via a transceiver, to retrieve a package. Here, the contact includes a message with an identifier of the IoT blank device. The package may be received, the package including an application. The package may be installed. The installation including registering the application with a message queue of the IoT blank device. The application may also be run after installation. Data from the application running on the IoT blank device may be received via a message queue. The data may then be transmitted to the cloud endpoint via the transceiver of the IoT blank device.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Atif Hussein, Trina Ward, Patricia Robb
  • Patent number: 10310868
    Abstract: A processor includes a core within a package and layers of programmable fabric within the same package as the core. The core includes logic to execute an instruction by loading a configuration file to one of the layers of programmable fabric. The configuration is to program an identified execution functionality. The execution functionality is to execute at least part of the instruction.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Leo A. Linsky
  • Patent number: 10313129
    Abstract: A processor of an aspect includes a decode unit to decode a keyed-hash message authentication code instruction. The keyed-hash message authentication code instruction is to indicate a message, to indicate at least one value that is to represent at least one of key information and key indication information, and to indicate a destination storage location. An execution unit is coupled with the decode unit. The execution unit, in response to the keyed-hash message authentication code instruction, is to store a message authentication code corresponding to the message in the destination storage location. The message authentication code is to be consistent with a keyed-hash message authentication code algorithm that is to use a cryptographic hash algorithm. The message authentication code is to be based on a cryptographic key associated with the at least one value. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Jason W. Brandt
  • Patent number: 10310565
    Abstract: Particular embodiments described herein provide for an electronic device that includes a flexible display and a support for the flexible display. The support includes a main support structure, at least one curve crease, and a curve region, wherein the curve region includes a curve support.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Aleksander Magi, Mark Angus MacDonald, Michael Ahrens
  • Patent number: 10310865
    Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Jiewen Yao, Vincent Zimmer, Nicholas Adams, Willard Wiseman, Giri Mudusuru, Nuo Zhang
  • Patent number: 10313842
    Abstract: One embodiment provides an apparatus. The apparatus includes a device. The device includes at least one transceiver. The device further includes transceiver selection logic to determine whether each of the at least one transceiver complies with transceiver regulations associated with a location of the device.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Keith Nolan, Mark Kelly
  • Patent number: 10313788
    Abstract: An example apparatus for detecting loudspeaker faults includes a switch detector to detect that a loudspeaker fault detection switch is enabled. The apparatus also includes an audio receiver to receive an echo energy threshold and audio from a microphone in a test area. The apparatus further includes an audio analyzer to detect that the echo energy threshold is not exceeded by an acoustic echo in the captured audio. The apparatus includes a fault generator to generate a loudspeaker fault in response to detecting the acoustic echo does not exceed the echo energy threshold.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Stanley Chang, Alan Yao
  • Patent number: 10313681
    Abstract: Various embodiments are generally directed to techniques for reducing processing and/or storage resource requirements for RDO in compressing motion video. A device to compress motion video includes a first cost calculator to derive a first bitcost value of using a quantized coefficient of a quantized coefficient block of a frame of a video in compressing the video, the first bitcost value based on a context model of a context-adaptive binary arithmetic coder (CABAC); and a second cost calculator to derive a second bitcost value of replacing the quantized coefficient with an alternate value derived from the quantized coefficient in compressing the video, the second bitcost value based on the context model. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: June 4, 2019
    Assignee: INTEL CORPORATION
    Inventors: Heon-Mo Koo, Atthar H. Mohammed, Thuan H. Pham
  • Patent number: 10311252
    Abstract: Technologies for managed code execution include a computing device having a processor with protection key support. The computing device sets a protection key register of the processor with permissions to disallow data access to any protection domain of the computing device and then executes a domain switch routine to switch to a managed applet. The managed applet is included in an applet protection domain, the domain switch routine is included in a switch protection domain, and a managed runtime environment is included in a normal protection domain. The domain switch routine sets the protection key register with permissions to disallow access to any protection domain other than the applet protection domain and then executes the managed applet. Other managed applets may be each be included in separate applet domains. Each managed applet may be a thread executed within a common process address space. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Xiaoning Li, Mingqiu Sun, David A. Koufaty, Ravi L. Sahita
  • Patent number: 10313888
    Abstract: This disclosure relates to a method for primary channel selection by a first access point type communication device (AP) of a group of APs, the method comprising: detecting, by the first AP, a central frequency location and a bandwidth of a primary channel selected by at least one second AP of the group of APs; selecting, by the first AP, a central frequency location and a bandwidth of a primary channel for the first AP, wherein the selection of the central frequency location and bandwidth of the primary channel for the first AP is based on the detected central frequency location and bandwidth of the primary channel for the at least one second AP.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Yaron Alpert
  • Patent number: 10312397
    Abstract: An Si/Ge SACM avalanche photodiodes (APD) having low breakdown voltage characteristics includes an absorption region and a multiplication region having various layers of particular thicknesses and doping concentrations. An optical waveguide can guide infrared and/or optical signals or energy into the absorption region. The resulting photo-generated carriers are swept into the i-Si layer and/or multiplication region for avalanche multiplication. The APD has a breakdown bias voltage of well less than 12 V and an operating bandwidth of greater than 10 GHz, and is therefore suitable for use in consumer electronic devices, high speed communication networks, and the like.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Yimin Kang, Han-Din Liu
  • Patent number: 10313918
    Abstract: Disclosed is a method for managing Internet Protocol Packet bundling comprising determining an operation of a real-time critical service (“RTCS”) on a mobile device; determining a data management indicator for the RTCS; where a RTCS is operating, and based on the data management indicator, determining a maximum number of Internet Protocol Packets for bundled delivery from a first layer of a protocol stack to a second layer of the protocol stack; receiving a number of Internet Protocol Packets totaling the maximum number of Internet Protocol Packets for bundled delivery; where the maximum number of Internet Protocol Packets for bundled delivery is greater than one, bundling the number of Internet Protocol Packets, and delivering the number of Internet Protocol Packets the first layer of the protocol stack to the second layer of the protocol stack.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel IP Corporation
    Inventors: Hans Juergen Leicht, Mohamed Hassan Helmy Khalil, Mohamed Amin Nassar
  • Patent number: 10306880
    Abstract: Systems, apparatuses, and/or methods to protect an entity. A detector may detect an animal proximate to an entity based on sensor data from a plurality of sensors. The plurality of sensors may be positioned, for example, on the entity. In addition, a protector may administer a mechanical repellant from a protection device to repel the animal proximate to the entity. The mechanical repellant may include, for example, an ultrasound wave, a vibration wave, and so on. Moreover, the mechanical repellant may be specific to a type of animal to repel the animal proximate to the entity. The mechanical repellant may further be harmless to the animal (or the entity) and/or inapplicable to at least one other animal in the environment.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Hong Wei Teh, Tomer Rider
  • Patent number: 10313769
    Abstract: Technologies for managing partially synchronized writes include a managed node. The managed node is to issue a write request to write a data block, on behalf of a workload, to multiple data storage devices connected to a network, pause execution of the workload, receive an initial acknowledgment associated with one of the multiple data storage devices, wherein the initial acknowledgement is indicative of successful storage of the data block, and resume execution of the workload after receipt of the initial acknowledgement and before receipt of subsequent acknowledgements associated with any of the other data storage devices. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Steven C. Miller
  • Patent number: 10313108
    Abstract: A processing system includes a processor to construct an input message comprising a target value and a nonce and a hardware accelerator, communicatively coupled to the processor, implementing a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash, the hardware accelerator is to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, calculate a plurality of speculative computation bits using a plurality of bits of the state data, and transmit the plurality of speculative computation bits to the processor.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Vikram B. Suresh, Sudhir K. Satpathy, Sanu K. Mathew
  • Patent number: 10313130
    Abstract: One embodiment provides a signer device. The signer device includes hash signature control logic and signer signature logic. The hash signature control logic is to retrieve a first nonce, to concatenate the first nonce and a message to be transmitted and to determine whether a first message representative satisfies a target threshold. The signer signature logic is to generate a first transmitted signature based, at least in part, on the first message representative, if the first message representative satisfies the target threshold. The hash signature control logic is to retrieve a second nonce, concatenate the second nonce and the message to be transmitted and to determine whether a second message representative satisfies the target threshold, if the first message representative does not satisfy the target threshold.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Rafael Misoczki, Steffen Schulz, Manoj R. Sastry, Santosh Ghosh, Li Zhao
  • Patent number: 10312986
    Abstract: Described are an eNB and a UE implementing a CSI-RS protocol. The eNB has an ordered set of antenna ports for a wireless communication channel with the UE, a first circuitry operable to compose CSI-RS configuration messages that assign to the UE various CSI-RS groups specifying one or more CSI-RS antenna ports, and a second circuitry to establish an ordered list of CSI-RS antenna ports. The UE has a set of antennas, a first circuitry operable to receive from the eNB various CSI-RS configuration messages assigning to it CSI-RS groups specifying one or more CSI-RS antenna ports, and a second circuitry operable to index CSI-RS antenna ports specified by the CSI-RS groups as an ordered list of CSI-RS antenna ports. The eNB may transmit CSI-RS to the configured UE, and the UE may perform channel state information measurements on the ordered list of CSI-RS antenna ports.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Alexei Vladimirovich Davydov, Alexander Alexandrovich Maltsev, Gregory Vladimirovich Morozov
  • Patent number: 10313240
    Abstract: Technologies for efficient network flow classification include a computing device that receives a network packet that includes a header. The computing device generates a vector Bloom filter (VBF) key as a function of the header and searches multiple VBFs for a VBF that matches the VBF key. Each VBF is associated with a flow sub-table that includes one or more flow rules. Each flow sub-table is associated with a mask length. If a matching VBF is found, the computing device searches the corresponding flow sub-table for a flow rule that matches a masked header of the network packet. If no matching VBF is found or if no matching flow rule is found, the computing device searches all of the flow sub-tables for a flow rule that matches the header. The computing device applies a flow action of a matching flow rule. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Sameh Gobriel, Wei Shen, Tsung-Yuan C. Tai, Ren Wang
  • Patent number: 10313260
    Abstract: An architecture and method for managing at least two distinct machines (or objects) in which resources are shared as a single entity (or object) in an agent-based system. The agent-based system comprising a controller, a local agent coupled to the controller, and at least one clustered machine. The at least one clustered machine includes at least two individual agents, the at least two individual agents sharing at least one shared resource/service. The system also includes a virtual non-persistent connection for coupling the at least two individual agents to the local agent. The at least one shared resource/service is accessed by the local agent through the virtual non-persistent connection using a virtual IP address to enable the at least two individual agents of the at least one clustered machine to be represented as a single object.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 4, 2019
    Assignee: INTEL CORPORATION
    Inventors: Marc D. Torrant, Paul Baleme
  • Patent number: 10313427
    Abstract: Technologies are presented that optimize application management on a computing device through contextual application archival and retrieval. A method of managing applications may include: learning contextual relevancy of one or more applications installed on a computing device to a user of the device and determining whether an application is no longer contextually relevant to the user. If the application is no longer contextually relevant, the device may send a request to an application management service to obtain and/or maintain the application; create a placeholder for the application at the device; and remove the application from the device. The device may monitor contextual inputs for relevancy of the archived application. If contextual relevancy is determined, the device may send a request to the service to provide the archived application or a replacement of the archived application to the device; receive the requested application; install the requested application; and remove the placeholder.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Igor Tatourian, Rita H Wouhaybi, Hong Li, Tobias M Kohlenberg, Adam Jordan
  • Patent number: 10313449
    Abstract: Embodiments of system and method configurations for providing provisioning information to a mobile device via a wireless network access point are generally described herein. In some examples, a communication session is established between a mobile device and a service provider to obtain provisioning information for wireless network connectivity via a designated access point (e.g., a “hotspot”). A HTTP session is established within the communication session to exchange registration information via a browser of the mobile device. Provisioning information is returned within the communication session in a Subscription Management Object (MO) in response to successful completion of the HTTP session. The subscription MO is provided outside of the browser and the HTTP session (but within the communication session) using mechanisms such as OMA-DM or SOAP-XML communications. The mobile device can then utilize the provisioning information from the subscription MO to associate with an appropriate hotspot.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel IP Corporation
    Inventors: Necati Canpolat, Venkata Vallabhu, Vivek G. Gupta
  • Patent number: 10313626
    Abstract: In one embodiment, an apparatus includes a processor circuit; a media distribution component for execution on the processor circuit to manage presentation of a media presentation on multiple electronic displays, the media presentation comprising a video part and an auxiliary data part, the auxiliary data part comprising sensor data corresponding to the video part, the media distribution component to manage presentation of the video part on an external display and the auxiliary data part on an integrated display. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: June 4, 2019
    Assignee: INTEL CORPORATION
    Inventor: Daniel Avrahami
  • Patent number: 10312594
    Abstract: An antenna device, wireless communication device, and method to provide wide banded antenna tuning. The antenna device is configured to include a higher frequency range antenna element, a lower frequency range antenna element, a resonance switch, and high and lower frequency range coupler elements. The antenna device provides a high frequency switch stage and a low frequency switch stage. The high frequency switch stage includes the antenna device being configured to resonate at one or more frequencies within a high impedance bandwidth and the low frequency switch stage includes the antenna device being configured to resonate at one or more frequencies within a low impedance bandwidth. The antenna device further includes impedance tuning circuitry to modify the impedance bandwidths of both the low and high frequency bandwidths. The antenna device is configured to separately perform impedance tuning for each of a transmit signal and a receive signal.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Simon Svendsen, Ole Jagielski
  • Publication number: 20190163641
    Abstract: An apparatus to facilitate page translation prefetching is disclosed. The apparatus includes a translation lookaside buffer (TLB), including a first table to store page table entries (PTEs) and a second table to store tags corresponding to each of the PTEs; and prefetch logic to detect a miss of a first requested address in the TLB during a page translation, retrieve a plurality of physical addresses from memory in response to the TLB miss and store the plurality of physical addresses as a plurality of PTEs in a first TLB entry.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventors: Niranjan Cooray, Nicolas Kacevas, David Standring
  • Publication number: 20190166292
    Abstract: Techniques related to removing haze from video are discussed. Such techniques include color converting a video frame from an input color space to a haze color space using a haze color detected in a previous frame, estimating pixel-wise haze amounts, de-hazing the video frame in the haze color space using the pixel-wise haze amounts, and color converting the de-hazed frame to the input color space.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 30, 2019
    Applicant: INTEL CORPORATION
    Inventor: Dmitry Grilikhes
  • Publication number: 20190166596
    Abstract: A RAN-based cellular integration architecture is described that eliminates or minimizes required core network support. A local access gateway (LA-GW) node, which may be a logical and physical node, may provide an interface, with a cellular base station, and may forward downlink and/or uplink local IP packets that are then redirected to the cellular link. Network Address Translation (NAT) and a “local access” field are used to support transmission of local access packets over the cellular link.
    Type: Application
    Filed: September 26, 2016
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventors: Jing Zhu, Nageen Himayat
  • Publication number: 20190164959
    Abstract: Described herein are quantum integrated circuit (IC) assemblies that include quantum circuit components comprising a plurality of qubits and control logic coupled to the quantum circuit components and configured to control operation of those components, where the quantum circuit component(s) and the control logic are provided on a single die. By implementing control logic on the same die as the quantum circuit component(s), more functionality can be provided on-chip, thus integrating more of signal chain on-chip. Integration can greatly reduce complexity and lower the cost of quantum computing devices, reduce interfacing bandwidth, and provide an approach that can be efficiently used in large scale manufacturing. Methods for fabricating such assemblies are also disclosed.
    Type: Application
    Filed: September 29, 2016
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventors: Nicole K. Thomas, Ravi Pillarisetty, Jeanette M. Roberts, Hubert C. George, James S. Clarke
  • Publication number: 20190164057
    Abstract: Embodiments are directed to mapping and quantification of neural network features for explainable artificial intelligence. An embodiment of one or more storage mediums includes instructions for evaluating contribution of lower level features to higher level features in a neural network, the evaluation including one or more of identification of links between lower level and higher level features, and quantification of contribution of lower level features to higher level features. An embodiment of one or more storage mediums includes instructions for determining support from one or more features for one or more inference decisions by a neural network; determining strength of support for each of the inference decisions; identifying one or more inference decisions with low stability based at least in part on the determined strength of support; and reevaluating the inference decisions that are identified as having low stability.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventor: KSHITIJ DOSHI
  • Publication number: 20190164077
    Abstract: Described herein are structures that include flux bias lines for controlling frequencies of qubits in quantum circuits. An exemplary structure includes a substrate, a qubit provided over a surface of the substrate, and a flux bias line provided below the surface of the substrate and configured to control the frequency of the qubit via a magnetic field generated as a result of a current flowing through the flux bias line. Methods for fabricating such structures are disclosed as well.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, Zachary R. Yoscovits, James S. Clarke, David J. Michalak
  • Publication number: 20190164290
    Abstract: Techniques related to implementing fully convolutional networks for semantic image segmentation are discussed. Such techniques may include combining feature maps from multiple stages of a multi-stage fully convolutional network to generate a hyper-feature corresponding to an input image, up-sampling the hyper-feature and summing it with a feature map of a previous stage to provide a final set of features, and classifying the final set of features to provide semantic image segmentation of the input image.
    Type: Application
    Filed: August 25, 2016
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventors: Libin Wang, Anbang Yao, Yurong Chen
  • Publication number: 20190165046
    Abstract: A memory device includes a plurality of memory cells, a first nonconductive separator material separating the memory cells and having a word line end and bit line end, a metal via separated from the plurality of memory cells by a second nonconductive separator material, and metal bit line electrically connecting the metal via with the plurality of memory cells. The memory cells include a phase change material layer, a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side, a metal silicon nitride layer on a surface of the bit line side of the first electrode layer. A bit line end surface of the first nonconductive separator material is at least partially free of contact with the metal silicon nitride layer.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventors: Nathan A. Wilkerson, Mihir Bohra
  • Publication number: 20190166281
    Abstract: Systems, apparatuses, and/or methods may define a priority of image memory traffic based on image sensor protocol metadata. For example, a metadata identifier may identify image sensor protocol metadata corresponding to an image sensor physical layer and/or an image sensor link layer. Moreover, a prioritizer may define a priority of the image memory traffic based on the image sensor protocol metadata. The priority may be used to control client access to dedicated memory and/or to shared memory.
    Type: Application
    Filed: June 1, 2017
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventor: Wesley J. Holland
  • Publication number: 20190164821
    Abstract: Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods are disclosed herein. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventor: Shruti Rajeev Jaywant
  • Publication number: 20190165152
    Abstract: Disclosed herein are quantum dot devices with patterned gates, as well as related computing devices and methods. For example, a quantum dot device may include gates disposed on a quantum well stack. In some embodiments, the gates may include a first gate with a first length; two second gates with second lengths arranged such that the first gate is disposed between the second gates; and two third gates with third lengths arranged such that the second gates are disposed between the third gates; and the first, second, and third lengths may all be different. In some embodiments, the gates may include a first set of gates alternatingly arranged with a second set of gates, spacers may be disposed between gates of the first set and gates of the second set, and gates in the first or second set may include a gate dielectric having a U-shaped cross-section.
    Type: Application
    Filed: June 10, 2016
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10303571
    Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Ning Wu, Xin Guo, Ramkarthik Ganesan, Pranav Kalavade, Robert Frickey
  • Patent number: 10303237
    Abstract: Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Baruch Schnarch
  • Patent number: 10301176
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Patent number: 10303984
    Abstract: An apparatus for visual search and retrieval using sematic information is described herein. The apparatus includes a controller, a scoring mechanism, an extractor, and a comparator. The controller is to segment an incoming video stream into a plurality of activity segments, wherein each frame is associated with an activity. The scoring mechanism is to calculate a score for each segment, wherein the score is based, at least partially, on a classification probability of each frame. The extractor is to extract deep features from a highest ranked segment, and the comparator is to determine the top-K neighbors based on the deep features.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Teahyung Lee, Krishna Kumar Singh, Myung Hwangbo
  • Patent number: 10303456
    Abstract: Technologies for performing energy efficient software distribution include a mesh node. The mesh node is to obtain fingerprint data of a plurality of other mesh nodes in a network. The mesh node is also to determine corresponding characteristics of the mesh nodes from the obtained fingerprint data, including an energy status of each of the mesh nodes. The mesh node is also to perform an analysis of a software update, determine, as a function of the analysis of the software update, one or more target mesh nodes of the plurality of mesh nodes for the software update, and determine a path through the mesh nodes to the one or more target mesh nodes as a function of the fingerprint data. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Simon Hunt, Ned M. Smith, Barry E. Huntley, Rita H. Wouhaybi
  • Patent number: 10303605
    Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Joseph Nuzman, Stanislav Shwartsman, Igor Yanover, Liron Zur
  • Patent number: 10306760
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 10303484
    Abstract: A method for line speed interconnect processing. The method includes receiving initial inputs from an input communications path, performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs, and performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs. The method further includes transmitting the resulting outputs out of the second stage at line speed.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 10306580
    Abstract: Systems and methods of enabling intersystem changes between 4G and 5G are described. The UE in single registration mode handles default EPS bearer contexts and PDU session contexts as if the N26 interface were supported before making the determination whether N26 interface is supported or not during an initial EPS Attach procedure. After determining that the N26 interface is unsupported, the UE maps active PDU session contexts to default EPS bearer contexts and modifies the PDU session context state from active to inactive before completing the intersystem change. The UE either acts as if the N26 interface were supported and loses all the PDN connections or PDU sessions during the intersystem change, or enters a modified single registration mode in which the states of the EPC and 5G system are partially isolated from each other during the intersystem change.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventor: Vivek G. Gupta
  • Patent number: 10303735
    Abstract: Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew
  • Patent number: 10306634
    Abstract: According to an example, a communication device is described comprising a receiver configured to receive a signal, a divider configured to divide the signal into signal components, an estimator configured to estimate, for each signal component, an expected processing error which is made when, instead of a first processing scheme, a second processing scheme is used to process the signal component, wherein the first has a higher processing effort than the second, a determiner configured to determine, for each signal component, whether to process the signal component by the first or by the second processing scheme based on the expected processing errors.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Holger Neuhaus, Rajarajan Balraj, Christian Faber, Bertram Gunzelmann