Abstract: Systems and methods for tone mapping of high dynamic range (HDR) images for high-quality deep learning based processing are disclosed. In one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. The execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.

Abstract: For example, an Access Point (AP) may be configured to process network slicing information including slice identification information and Service Level Agreement (SLA) information, wherein the slice identification information is to identify one or more Quality of Service (QoS) network slices. For example, the AP may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more QoS network slices, and to transmit a network slicing advertisement including network slicing assignment information to indicate an assignment of the one or more radio resource allocations to the one or more QoS network slices.

Abstract: Technologies for performing sensor fusion include a compute device. The compute device includes circuitry configured to obtain detection data indicative of objects detected by each of multiple sensors of a host system. The detection data includes camera detection data indicative of a two or three dimensional image of detected objects and lidar detection data indicative of depths of detected objects. The circuitry is also configured to merge the detection data from the multiple sensors to define final bounding shapes for the objects.

Abstract: Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.

Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.

Abstract: Methods, systems, and articles are described herein related to video coding. The method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. The method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. This method comprises detecting whether or not the block has an illegal block partition. Also, the method comprises generating second partition data to indicate the illegal block partition of the block is to be ignored. Further, the method includes decoding the block at least according to the second partition data.

Abstract: A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.

Abstract: Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.

Abstract: Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.

Abstract: A graph neural network (GNN) model is used in a scheduling process for compiling a deep neural network (DNN). The DNN, and parameter options for scheduling the DNN, are represented as a graph, and the GNN predicts a set of parameters that is expected to have a low cost. Using the GNN-based model, a compiler can produce a schedule for compiling the DNN in a relatively short and predictable amount of time, even for DNNs with many layers and/or many parameter options. For example, the GNN-based model reduces the overhead of exploring every parameter combination and does not exclude combinations from consideration like prior heuristic-based approaches.

Abstract: For example, an apparatus may include a segment parser to parse scrambled data bits of a PPDU into a first plurality of data bits and a second plurality of data bits, the PPDU to be transmitted in an OFDM transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first OFDM MCS for transmission over the first channel in the first frequency band; and a second baseband block to encode and modulate the second plurality of data bits according to a second OFDM MCS for transmission over the second channel in the second frequency band.

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

Abstract: Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.

Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.

Abstract: Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

Abstract: In an embodiment, a processor comprises: an execution circuit to execute instructions; at least one cache memory coupled to the execution circuit; and a table storage element coupled to the at least one cache memory, the table storage element to store a plurality of entries each to store object metadata of an object used in a code sequence. The processor is to use the object metadata to provide user space multi-object transactional atomic operation of the code sequence. Other embodiments are described and claimed.

Abstract: Folded integer multiplier (FIM) circuitry includes a multiplier configurable to perform multiplication and a first addition/subtraction unit and a second addition/subtraction unit both configurable to perform addition and subtraction. The FIM circuitry is configurable to determine each product of a plurality of products for a plurality of pairs of input values having a first number of bits by performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction, and performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits. The plurality of multiplication operations includes a first number of multiplication operations, and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations.

Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

Abstract: Disclosed embodiments provide a handover prediction scheme that is based on contextual awareness of a compute node, such as a mobile device. The contextual information is used to predict network availability in a predicted target location, which is an area that a compute node is likely to travel. The use of sensors embedded in or accessible by the compute node may be used to carry out aspects of the embodiments. A reinforcement learning recommendation model is used to determine an optimal network, radio access technology, and/or network access node to connect with ahead of arriving at the predicted target location at a predicted arrival time. Other embodiments are described and/or claimed.

Abstract: In one embodiment, an apparatus comprises circuitry, wherein the circuitry is configured to: receive, via a communications network, context information for a first set of one or more edge devices, wherein the context information identifies an operating environment of the first set of edge devices based on information from one or more sensors; receive, via the communications network, workload information for a second set of one or more edge devices; determine workload assignments for the first set of edge devices based on the context information for the first set of edge devices and based on the workload information for the second set of edge devices; and transmit, via the communications network, the workload assignments to the first set of edge devices.

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

Abstract: Various embodiments generally may relate to Load Balancing Optimization (LBO) and Mobility Robustness Optimization (MRO). Some embodiments of this disclosure are directed to the following 5G SON solutions: use cases and requirements for the management of distributed LBO and centralized LBO; procedures for the management of distributed LBO and centralized LBO; and management services and information needed to support the management of distributed LBO and centralized LBO.

Abstract: An extremely high-throughput (EHT) station (STA) may encode an EHT PPDU for transmission on a plurality of subchannels. The EHT STA may determine a spectral mask to apply to the EHT PPDU prior to transmission of the EHT PPDU. When preamble puncturing is performed, the EHT STA may apply an overall spectral mask to the EHT PPDU prior to transmission. The overall spectral mask may be based on an interim spectral mask and a preamble-puncture spectral mask. The subchannels may be in a 6 GHz band and the EHT STA may determine if preamble puncturing is to be performed for one or more of the subchannels based on a presence of incumbents in the one or more of the subchannels, although the scope of the embodiments is not limited in this respect.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a sandwich plate construction heatsink. The sandwich plate construction heatsink can include a cold plate, one or more heat pipes over the cold plate, and a top plate over the one or more heat pipes. The cold plate can include a channel to accommodate the one or more heat pipes and/or the top plate can include a channel to accommodate the one or more heat pipes. The cold plate can be over a heat source in the electronic device.

Abstract: A computer-readable storage medium stores instructions for execution by one or more processors of a UE. The instructions configure the UE for small data transmission (SDT) in a 5G NR network and cause the UE to perform operations comprising detecting while in an RRC_Inactive state, a radio link failure during a first SDT of UL data to a base station. A secure key for a second SDT is generated based on the radio link failure. A configuration message including an indication of the second SDT is transmitted to the base station. A response message including a UL grant is received from the base station. The UL data is encoded for the second SDT using the secure key. The second SDT is performed using the UL grant while the UE is in the RRC_Inactive state.

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

Abstract: Methods, systems and apparatuses may provide for technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer. The technology may also determine an event type associated with the request and conduct the request based on the event type.

Abstract: Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.

Abstract: Techniques are provided for detection of laser-based audio injection attacks. A methodology implementing the techniques according to an embodiment includes calculating cross correlations between signals received from microphones of an array of two or more microphones. The method also includes identifying time delays associated with peaks of the cross correlations, and magnitudes associated with the peaks of the cross correlations. The method further includes calculating a time alignment metric based on the time delays and calculating a similarity metric based on the magnitudes. The method further includes generating a first attack indicator based on a comparison of the time alignment metric to a first threshold and generating a second attack indicator based on a comparison of the similarity metric to a second threshold. The method further includes providing warning of a laser-based audio attack based on the first attack indicator and/or the second attack indicator.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Abstract: An apparatus and system to enable dynamic offloading and execution of compute tasks are described. In split CU-DU RAN architectures, the CU-CP is connected with multiple compute control functions (CF) and service functions (SF) that have different computing hardware/software capabilities. Different architectures depend on whether the SF is collocated with the CU-UP, the CU-UP and SF only serve compute messages, a compute message is supplied directly to the CU-UP or also traverses the CU-CP. In response to reception from a UE of a compute message containing data for computation being sent to the CU-CP through the DU, the CU-CP sends the data to the SF with identifiers and sends the result to the UE.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

Abstract: Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.

Abstract: One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling anti-aliasing operation via a mixed precision convolutional neural network. The set of processing resources include circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, jitter offset data, and velocity data, pre-process the set of data to generate pre-processed data, provide pre-processed data to a feature extraction network of the neural network model and an output block of the neural network model, process the first pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, output tensor data from the feature extraction network to the output block, and generate an anti-aliased output frame via the output block based on the current frame data and the tensor data output from the feature extraction network.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.

Abstract: Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.

Abstract: One or more non-transitory computer-readable media with instructions stored thereon, wherein the instructions are executable to cause one or more processor units to responsive to a data clear command issued by a tenant of a cloud service provider, issue a plurality of write commands to storage locations utilized by the tenant, the write commands to write a value based on an input provided by the tenant to the storage locations; and provide data read from at least a subset of the storage locations for attestation by the tenant of performance of the data clear command.

Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

Abstract: For example, a wireless communication device may be configured to determine a Concurrent Multiple Band (CMB) routing scheme based on Quality of Service (QoS) requirement information and network condition information, the CMB routing scheme to route a plurality of application streams to a plurality of radios of the wireless communication device for wireless communication over a plurality of wireless communication bands, the plurality of application streams corresponding to one or more applications to be executed by the wireless communication device; and to route the plurality of application streams to the plurality of radios by determining, based on the CMB routing scheme, to which radio of the plurality of radios to route the application stream of the plurality of application streams.