Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

Abstract: An integrated circuit (IC) device includes a device substrate with front- and backside IC dies and an integrated heat spreader over the backside die. The heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. The backside heat spreader may include a mask layer over a thermally conductive layer. The IC device may include or be coupled to second substrate (such as a motherboard). The backside heat spreader may be thermally coupled to a heat spreader or heat sink by vias through the second substrate. The backside heat spreader may enclose the backside IC die in an electrically conductive cage.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for foldable thermal ground planes for electronic devices. An example an apparatus to cool an electronic device includes a first plate; a second plate; a plurality of first pillars extending between the first plate and the second plate, the plurality of first pillars having a first shape; a plurality of second pillars extending between the first plate and the second plate, the plurality of second pillars having a second shape, the second shape different than the first shape; and a hinge separating the apparatus into a first section and a second section, the plurality of second pillars in the hinge.

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

Abstract: A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. Metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. Metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); and a substrate layer on the surface of the glass layer, the substrate layer including a dielectric material, wherein the dielectric material includes an epoxy having thermal isomeric linkages, non-thermal isomeric linkages, and non-thermal isomeric epoxy monomers, and the thermal isomeric linkages including a cis-dibenzocyclooctane (DBCO) moiety or a tetra derivative DBCO moiety. In some embodiments, the dielectric material includes an epoxy having thermal isomeric epoxy monomers including a cis-DBCO moiety or a tetra derivative DBCO moiety, non-thermal isomeric epoxy monomers, and non-thermal isomeric linkages.

Abstract: A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the IC die structure to the substrate structure. A biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. The inner region may improve fine alignment, particularly if there is a significant amount of tilt between a bonding surface of the IC die structure and a bonding surface of the substrate structure during placement. The inner region may, for example, facilitate the confinement of two or more droplets on the bonding regions. Inner or outer regions of a biphilic structure may be segmented or contiguous and intersecting IC die edges may also be non-orthogonal.

Abstract: DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and below the IC die; and a gap within the dielectric material and extending around the metallization pattern.

Abstract: A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding process a biphilic surface on the IC die structure or substrate structure may facilitate liquid droplet-based fine alignment of the IC die structure to a host structure. Prior to bonding, the surface finish may be applied upon a top surface of metallization features and may inhibit oxidation of the top surface exposed to the liquid droplet.

Abstract: Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid bonding on the bottom surface of the die. Embedded bridges or chiplets or not used for die-to-die I/O routing, which can free up space for more through-dielectric vias to provide power and ground connections to the die, which can provide for improved power delivery.

Abstract: Techniques and mechanisms for forming a gate dielectric structure and source or drain (S/D) structures on a monolayer channel structure of a transistor. In an embodiment, the channel structure comprises a two-dimensional (2D) layer of a transition metal dichalcogenide (TMD) material. During fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to produce a conductive material. While a first portion of the dielectric material is covered by a patterned structure, a second portion of the dielectric material is exposed to a plasma treatment to form a source or dielectric (S/D) electrode structure that adjoins the first portion. In another embodiment, the dielectric material is an oxide of a Group V-VI transition metal.

Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.

Abstract: An apparatus to facilitate conversion operations and special value use cases supporting 8-bit floating point format in a graphics architecture is disclosed. The apparatus includes a processor comprising a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction to cause the processor to perform conversion operation corresponding to an 8-bit floating point format operand; a scheduler to schedule the decoded instruction and provide input data for an input operand of the conversion operation indicated by the decoded instruction; and conversion circuitry to execute the decoded instruction to perform the conversion operation to convert the input operand to an output operand in accordance with the 8-bit floating point format operand, the conversion circuitry comprising hardware circuitry to rescale, normalize, and convert the input operand to the output operand.

Abstract: Technologies for diamond composite materials are disclosed. In one embodiment, field-assisted sintering technology (FAST) is used to create a diamond composite material that includes diamond particles, copper, and chromium. The chromium can help bond the copper and the diamond particles. The diamond composite material has a high thermal conductivity, such as 500-1,000 W/(m·K). In one embodiment, the diamond composite material may be used in an integrated heat spreader in an integrated circuit component. In other embodiments, the diamond composite material may be used in a heat sink, a cold plate, an internal frame, a chassis, etc.

Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.

Abstract: A semiconductor package carrier used to support a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) as the semiconductor package is moved from a shipping tray to a land grid array (LGA) socket during assembly of an electronic device. The semiconductor package carrier including a carrier body including a plurality of support structures arranged to support a portion of the semiconductor package. The semiconductor package carrier further including a locking structure moveable between a first position and a second position, wherein the first position allows the support structures to receive the semiconductor package and the second position secures the semiconductor package to the carrier body. In some embodiments, the semiconductor package carrier may also include a thermal interface material (TIM) breaker to facilitate removal of a heatsink from the semiconductor package. Other embodiments are described and claimed.

Abstract: Alignment markers are created on a carrier wafer prior to attachment of integrated circuit dies to the carrier wafer. The alignment markers can be used in aligning integrated circuit dies to the carrier wafer during attachment of the integrated circuit dies to the carrier wafer. A reconstituted wafer can be created from the integrated circuit dies attached to the carrier wafer and the alignment markers are part of the reconstituted wafer. The alignment markers can further be used to align a wafer bonding layer to the reconstituted wafer. The wafer bonding layer can be used in attaching the reconstituted wafer to an interposer, another wafer, or another microelectronic structure. The alignment markers are located outside an outer lateral boundary of the integrated circuit dies (such as between integrated circuit dies) and are not connected to any metal lines in the integrated circuit dies in the reconstituted wafer.

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more antennas, interconnects, inductors, capacitors, or transformers. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

Abstract: In one embodiment, an integrated circuit device includes a substrate and a component coupled to the substrate. The substrate includes first reservoirs comprising Gallium-based liquid metal (LM), second reservoirs, first channels between the first reservoirs, and second channels between the second reservoirs and respective first reservoirs. The component includes circuitry and conductive contacts connected to the circuitry. Each contact defines a cavity and a portion of each conductive contact is within a respective first reservoir of the substrate such that it is in contact with the LM in the first reservoir. The component further includes dielectric lines between the conductive contacts, and each dielectric line is at least partially within a respective first channel of the substrate.

Abstract: In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the second bonding structures are arranged in a layout that is offset from the layout of the second substrate. The process further includes partially bonding the first substrate to the third substrate, which includes bonding a second subset of IC components on the first substrate to respective bonding structures on the third substrate.

Abstract: Techniques and mechanisms for a transition metal dichalcogenide (TMD) material to be grown on one structure, and then transferred to a different structure. In an embodiment, one or more monolayers of a TMD material are grown on a workpiece comprising a substrate, a growth layer, and a release layer. A material of the substrate is transparent to a wavelength of a laser light, wherein the release layer is opaque to said wavelength. The resulting material stack is then coupled to a target structure, after which a laser ablation is performed to remove some or all of the release layer from between the substrate and the growth layer. The ablation enables the substrate to be separated from the one or more monolayers. In an embodiment, a residue on a surface of the one or more TMD monolayers is an artefact of the layer transfer process.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. A first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. A second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. Subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.

Abstract: An integrated circuit (IC) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. A functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. The IC device may include multiple such functional blocks spanning lithographic fields. The lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as registration marks and metrology structures. The multiple lithographic fields may be or include high numerical aperture extreme ultraviolet lithographic fields. The lithographic seam may interface with wafer finishing collaterals (such as guard rings).

Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer comprising at least one integrated circuit (IC) component, the third layer comprising at least one dielectric material; and using a laser to weaken the first layer to facilitate separation of the second layer from the substrate.

Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.

Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.

Abstract: Techniques for dynamic cache fill prioritization are described. In an embodiment, an apparatus includes a cache at a mid-level of a cache hierarchy; and a mid-level cache (MLC) unit including the cache, a local queue to store MLC lookup requests, an external queue to store MLC fill requests, and an MLC access control hardware. The MLC access control hardware is to dynamically switch prioritization of servicing the MLC lookup requests versus servicing the MLC fill requests.

Abstract: A ferrule of an optical connector device is to accept one or more optical fibers in one or more fiber holes of the ferrule, the ferrule is formed from a dielectric material. The ferrule includes a face to interface with an optical socket of another device, where ends of the one or more optical fibers are exposed at the face to communicate photon signals with another device. The ferrule further includes alignment features formed in the dielectric layer to align the ends of the one or more optical fibers with one or more waveguides of the other device.

Abstract: A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.

Abstract: Techniques for a coaxial inductor in a glass core are disclosed. In an illustrative embodiment, an inductor is positioned in a cavity of a glass core. The inductor includes a conductive via extending through the glass core surrounded by a magnetic material. A buffer layer is positioned between the edges of the cavity of the glass core and the inductor. The buffer can prevent or mitigate any stress caused by changes in temperature and different coefficients of thermal expansion of the glass core and the inductor. The inductor may form part of a fully integrated voltage regulator (FIVR), which provides a stable voltage source to a semiconductor die such as a processor.

Abstract: Technologies for an optical interposer with actuator beams are disclosed. In one embodiment, an integrated circuit package includes an optical interposer and a photonics integrated circuit (PIC) die. The optical interposer includes actuator beams and waveguides embedded in the actuator beams. An electrical trace is disposed on the actuator beams. In use, current can pass through the electrical trace, expanding the trace through thermal expansion. The trace expands more than the actuator beam underneath it, causing the actuator beam and the waveguides to be deflected. In this manner, the waveguides in the optical interposer can be positioned to align to waveguides in the PIC die.

Abstract: An example apparatus includes memory; machine-readable instructions; and at least one programmable circuit to at least one of execute or instantiate the machine-readable instructions to at least adjust a frequency of a clock signal of the memory based on workload demands of a processor circuit.

Abstract: Systems and methods include establishing a cryptographically secure communication between an application module and an audio module. The application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. The establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.

Abstract: Technologies for thermal plugs in photonic integrated circuit (PIC) dies are disclosed. In an illustrative embodiment, several thermal plugs extend from contact pads in a PIC die, through a dielectric layer, to a waveguide layer. The thermal plugs can carry heat at a higher rate than the surrounding dielectric layer, increasing the heat transfer through the PIC die. The PIC die may be mounted on an electronic integrated circuit (EIC) die in an integrated circuit component. The PIC die can transfer heat from the EIC die, through the PIC die, and to another component such as an integrated heat spreader, lowering the temperature of the EIC die. The thermal plugs can increase the heat transfer through the PIC die.

Abstract: In one embodiment, an integrated circuit structure includes a first transistor device comprising a first gate stack and a second transistor device comprising a second gate stack. The second transistor device is spaced a first distance laterally from the first transistor device. The structure further includes a dielectric region between the first gate stack and the second gate stack. The dielectric region is spaced a second distance laterally from the first transistor device, where the first distance is substantially twice the second distance.

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The cross-linked material hydrophobic structures contain the liquid droplet for alignment and are resistant to plasma treatment prior to bonding.

Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.

Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.

Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Abstract: In one embodiment, an apparatus includes a processor comprising at least one core to execute instructions of a plurality of virtual machines (VMs) and a virtual machine monitor (VMM), and a cryptographic engine to protect data associated with the plurality of VMs through use of a plurality of private keys and a trusted transformer key, where each of the plurality of private keys are to protect program instructions and data of a respective VM and the trusted transformer key is to protect management structure data for the plurality of VMs. The processor is further to provide, to the VMM, read and write access to the management structure data through an untrusted transformer key.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.

Abstract: A mechanism is described for facilitating cinematic space-time view synthesis in computing environments according to one embodiment. A method of embodiments, as described herein, includes capturing, by one or more cameras, multiple images at multiple positions or multiple points in times, where the multiple images represent multiple views of an object or a scene, where the one or more cameras are coupled to one or more processors of a computing device. The method further includes synthesizing, by a neural network, the multiple images into a single image including a middle image of the multiple images and representing an intermediary view of the multiple views.

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.

Abstract: Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.