Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Circuitry and methods for spatially unique and location independent persistent memory encryption
    Patent number: 11954047
    Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Mahesh Natu, Anand K. Enamandram, Manjula Peddireddy, Robert A. Branch, Tiffany J. Kasanicky, Siddhartha Chhabra, Hormuzd Khosravi
  • Self-equalized and self-crosstalk-compensated 3D transmission line architecture with array of periodic bumps for high-speed single-ended signal transmission
    Patent number: 11955436
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song, Stephen Hall
  • Dual bayesian encoding-decoding technique for text to code transformations
    Patent number: 11954462
    Abstract: Methods, apparatus, and software for implementing dual Bayesian encoding-decoding for text-to-code transformations. In one aspect, a multi-model probabilistic source code model employing dual Bayesian encoder-decoder models is used to convert natural language (NL) inputs (aka requests) into source code. An NL input is processed to generate a Probabilistic Distribution (PD) of Source code (SC) tokens in an SC token sequence and a PD of Abstract Syntax Tree (AST) tokens in an AST token sequence, wherein each SC token is associated with a respective AST token, and each of the SC and AST tokens have a respective PD. One or more fixing rules are applied to one or more tokens SC tokens that are identified as needing fixing, wherein the fixing rule are selected in consideration of the PDs of the SC tokens and the PDs of their associated AST tokens.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Alejandro Ibarra Von Borstel, Fernando Ambriz Meza, David Israel Gonzalez Aguirre, Walter Alejandro Mayorga Macias, Rocio Hernandez Fabian
  • Fan out package with integrated peripheral devices and methods
    Patent number: 11955395
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Dynamic offline end-to-end packet processing based on traffic class
    Patent number: 11956156
    Abstract: Methods and apparatus for dynamic offline end-to-end packet processing based on traffic class. An end-to-end connection is set up between an application on a client including a processor and host memory and an application on a remote server. An offline packet buffer is allocated in host memory. While the processor and/or a core on with the client application is executed is in a sleep state, the client is operated in an interrupt-less and polling-less mode as applied to a predetermined traffic class. Under the mode, a Network Interface Controller (NIC) at the client receives network traffic from the remote server and determines whether the network traffic is associated with the predetermined traffic class. When it is, the NIC writes packet data extracted from the network traffic to an offline packet buffer. Descriptors are generated and provided to the NIC to inform the NIC of the location and size of the offline packet buffer.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Akhilesh S. Thyagaturu, Vinodh Gopal
  • Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric
    Patent number: 11955532
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
  • Passivation layers for thin film transistors and methods of fabrication
    Patent number: 11955560
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Package stacking using chip to wafer bonding
    Patent number: 11955462
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
  • Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches
    Patent number: 11955448
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Jung Kyu Han, Hongxia Feng, Xiaoying Guo, Rahul N. Manepalli
  • Wireless communication technology, apparatuses, and methods
    Patent number: 11955732
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Source or drain structures with high phosphorous dopant concentration
    Patent number: 11955482
    Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Robert Ehlert, Timothy Jen, Alexander Badmaev, Shridhar Hegde, Sandrine Charue-Bakker
  • Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links
    Patent number: 11954360
    Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Narasimha Lanka, Kuljit Bains, Lohit Yerva
  • Ultra small molded module integrated with die by module-on-wafer assembly
    Patent number: 11955434
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
  • Apparatus and method for error reduction in distributed quantum systems via fusing-and-decomposing gates
    Patent number: 11954563
    Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 9, 2024
    Assignee: INTEL CORPORATION
    Inventors: Nicolas Sawaya, Anne Matsuura, Justin Hogaboam
  • Equalization and estimation processing in wireless devices
    Patent number: 11956104
    Abstract: Millimeter-wave (mmWave) and sub-mmWave technology, apparatuses, and methods that relate to transceivers and receivers for wireless communications are described. The various aspects include an apparatus of a communication device including one or more antennas configured to receive an RF signal and an ADC system. The ADC system includes a 1-bit ADC configured to receive the RF signal, and an ADC controller circuitry configured to measure a number of positive samples in the received RF signal for a plurality of thresholds of the 1-bit ADC, estimate receive signal power associated with the received RF signal based on the measured number of positive samples, determine a direct current (DC) offset in the received RF signal using the estimated received signal power, and adjust the received RF signal based on the determined DC offset.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Oner Orhan, Hosein Nikopour, Mehnaz Rahman, Ivan Simoes Gaspar, Shilpa Talwar, Stefano Pellerano, Claudio Da Silva, Namyoon Lee, Yo Seb Jeon, Eren Sasoglu
  • Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
    Patent number: 11954063
    Abstract: Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an addition to a result of the multiply operation, and apply a rectified linear unit function to a result of the addition.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram, Varghese George, Darin Starkey, Guei-Yuan Lueh
  • Components for millimeter-wave communication
    Patent number: 11955684
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing
  • Methods and apparatus for machine learning-guided compiler optimizations for register-based hardware architectures
    Patent number: 11954466
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning based on an output of a query to a machine learning (ML) model, in response to determining the search tree is in need of pruning, prune the search tree at the current position, in response to applying the selected register-based compiler transformation to the source code, generate a code variant, calculate a score associated with the source code at the current position in the search tree, and update parameters of the machine learning (ML) model to include the calculated score.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Anand Venkat, Justin Gottschlich, Niranjan Hasabnis
  • Enhanced traffic indications for multi-link wireless communication devices
    Patent number: 11956663
    Abstract: This disclosure describes systems, methods, and devices related to traffic indications for multi-link devices (MLDs). A device may generate a first traffic indication map (TIM) with a first bitmap including a first indication that traffic is to be sent by a first access point (AP) device of the MLD to a first non-AP device of a second MLD using a first communication link. The device may generate a second TIM with a second bitmap including a second indication that no traffic is to be sent by a second AP device of the MLD to a second non-AP device of the second MLD using a second communication link. The device may send, using the first communication link, the beacon, the beacon including the first TIM and the second TIM. The device may send, using the first communication link, a data frame to the first non-AP device of the second MLD.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Alexander Min, Laurent Cariou, Minyoung Park, Po-Kai Huang
  • Object and cacheline granularity cryptographic memory integrity
    Patent number: 11954045
    Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
  • Differential on-chip loop antenna
    Patent number: 11955728
    Abstract: Aspects of the embodiments are directed to an on-chip loop antenna and methods of manufacturing the same. In some embodiments, the on-chip loop antenna is in an integrated circuit (IC) die. The IC die comprises metal loops substantially centered around a core region of the IC die in a metallization stack of the IC die, a dielectric between spaces of the metal loops, an electric circuit in the core region electrically connected to the metal loops with an interconnect, and a ground plane in the metallization stack electrically connected to the loops with a first plurality of vias and to the electric circuit with a second plurality of vias. The first plurality of vias is different from the second plurality of vias, and the electric circuit includes an inductor. In some embodiments, the on-chip loop antenna can be carried by a semiconductor package.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Nir Weisman, Omer Asaf, Eyal Goldberger
  • Stackable in-line filter modules for quantum computing
    Patent number: 11957066
    Abstract: Embodiments of the present disclosure describe quantum circuit assemblies that include one or more filter modules integrated in a package with a quantum circuit component having at least one qubit device. Integration may be such that both the quantum circuit component and the filter module(s) are at least partially inside a chamber formed by a radiation shield structure that is configured to attenuate electromagnetic radiation incident on the quantum circuit component and the filter module(s). Placing filter modules under the protection provided by the radiation shield structure may boost coherence of the qubits. Some example filter modules may include filter(s) configured to convert electromagnetic radiation to heat and filter(s) configured to perform bandpass filtering. Modular blocks of in-line filters inside the shielded environment may allow to route signals to the quantum circuit component with reduced noise and speed up installation of a complete quantum computer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Florian Luthi, Lester Lampert
  • Apparatus and method for two-stage lossless data compression, and two-stage lossless data decompression
    Patent number: 11955995
    Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: James Guilford, Vinodh Gopal, Daniel Cutter, Kirk Yap, Wajdi Feghali, George Powley
  • Two-stage bake photoresist with releasable quencher
    Patent number: 11955343
    Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Marie Krysak, James M. Blackwell, Florian Gstrein, Kent N. Frasure
  • System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis
    Patent number: 11953962
    Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Daniel J. Ragland, Guy M. Therien, Ankush Varma, Eric J. DeHaemer, David T. Mayo, Ariel Gur, Yoav Ben-Raphael, Mark P. Seconi
  • Apparatus, method, and system for collecting cold pages
    Patent number: 11954356
    Abstract: Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Qiuxu Zhuo, Anthony Luck
  • Apparatuses, methods, computer programs, and data carriers for indicating and detecting atomic operations
    Patent number: 11954465
    Abstract: An apparatus comprising at least one interface configured to read one or more high-level code instructions; and at least one processor configured to read the one or more high-level code instructions using the interface, determine atomic operations in the high-level code instructions, and translate the one or more high-level code instructions into assembly code instructions, wherein atomic operations are indicated in the assembly code instructions based on the atomic operations in the high-level code instruction.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Alexei Katranov, Stanislav Bratanov
  • Technologies for dynamically sharing remote resources across remote computing nodes
    Patent number: 11954528
    Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez, Harald Servat
  • DEVICE, METHOD, AND SYSTEM TO DETERMINE A COUNT OF RETIRED PREFETCH INSTRUCTIONS
    Publication number: 20240111656
    Abstract: Techniques and mechanisms for circuitry of a processor to determine a count of prefetch instructions which have been retired, or are designated for retirement. In an embodiment, a performance monitoring unit (PMU) monitors the execution of an instruction sequence by a core of said processor. The PMU detects the retirement of a first instruction, and further makes a first determination that the instruction is of a prefetch instruction type. Based on the first determination, counter circuitry of the processor updates a count of one or more instruction retirements, wherein each such retired instruction is of the prefetch instruction type. The PMU further makes a second determination that another retired second instruction is of a non-prefetch instruction type. In another embodiment, the counter circuitry prevents any updating of that same count based on the second determination.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Ahmad Yasin, Anton Hanna, Yuval Alon, Amandeep Kaur
  • HARDWARE PROCESSOR HAVING MULTIPLE MEMORY PREFETCHERS AND MULTIPLE PREFETCH FILTERS
    Publication number: 20240111679
    Abstract: Techniques for prefetching by a hardware processor are described. In certain examples, a hardware processor includes execution circuitry, cache memories, and prefetcher circuitry. The execution circuitry is to execute instructions to access data at a memory address. The cache memories include a first cache memory at a first cache level and a second cache memory at a second cache level. The prefetcher circuitry is to prefetch the data from a system memory to at least one of the plurality of cache memories, and it includes a first-level prefetcher to prefetch the data to the first cache memory, a second-level prefetcher to prefetch the data to the second cache memory, and a plurality of prefetch filters. One of the prefetch filters is to filter exclusively for the first-level prefetcher. Another of the prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher.
    Type: Application
    Filed: October 1, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Seth Pugsley, Mark Dechene, Ryan Carlson, Manjunath Shevgoor
  • ETCH STOP LAYER FOR METAL GATE CUT
    Publication number: 20240113106
    Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes (i) first source and drain regions, (ii) a first body including semiconductor material laterally extending between the first source and drain regions, (iii) a first sub-fin below the first body, and (iv) a first gate structure on the first body. The second device includes (i) second source and drain regions, (ii) a second body including semiconductor material laterally extending from the second source and drain regions, (iii) a second sub-fin below the second body, and (iv) a second gate structure on the second body. A second dielectric material is laterally between the first and second sub-fins. A third dielectric material is laterally between the first and second sub-fins, and above the second dielectric material. A gate cut including first dielectric material is laterally between the first and second gate structures, and above the third dielectric material.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sukru Yemenicioglu, Nikhil J. Mehta, Leonard P. Guler, Daniel J. Harris
  • CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING
    Publication number: 20240111353
    Abstract: Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Samuel Coward, Theo Drane, George A. Constantinides, Emiliano Morini
  • FORMING METAL GATE CUTS USING MULTIPLE PASSES FOR DEPTH CONTROL
    Publication number: 20240113105
    Abstract: Techniques are provided herein to form semiconductor devices that include gate cuts with different widths (e.g., at least a 1.5× difference in width) but substantially the same height (e.g., less than 5 nm difference in height). A given gate structure extending over one or more semiconductor regions may be interrupted with any number of gate cuts that each extend through an entire thickness of the gate structure. According to some embodiments, gate cuts of a similar first width are formed via a first etching process while gate cuts of a similar second width that is greater than the first width are formed via a second etching process that is different from the first etching process. Using different etch processes for gate cuts of different widths maintains a similar height for the gate cuts of different widths.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Alison V. Davis, Bern Youngblood, Reza Bayati, Swapnadip Ghosh, Matthew J. Prince, Jeffrey Miles Tan
  • HIGH ENDURANCE SUPER-LATTICE ANTI-FERROELECTRIC CAPACITORS
    Publication number: 20240114695
    Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to anti-ferroelectric capacitors having a cerium oxide doped hafnium zirconium oxide based anti-ferroelectric are described. A capacitor includes layers of hafnium oxide, cerium oxide, and zirconium oxide between metal electrodes. The cerium of the cerium oxide provides a mid gap state to protect the hafnium zirconium oxide during operation.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Nazila Haratipour, Christopher Neumann, Shriram Shivaraman, Brian Doyle, Sarah Atanasov, Bernal Granados Alpizar, Uygar Avci
  • APPARATUS, SYSTEM, AND METHOD OF A MULTI-MODE POWER AMPLIFIER
    Publication number: 20240113670
    Abstract: For example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. For example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. For example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: INTEL CORPORATION
    Inventors: Ofir Degani, Naor Roi Shay, Assaf Ben-Bassat, Limor Zohar, Yishai Eilat
  • SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES
    Publication number: 20240112970
    Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Hanyu Song, Vinith Bejugam, Yonggang Li, Gang Duan, Aaron Garelick
  • CAPACITOR STRUCTURE EMBEDDED WITHIN SOURCE OR DRAIN REGION
    Publication number: 20240113101
    Abstract: Techniques are provided herein to form a semiconductor device that has a capacitor structure integrated with the source or drain region of the semiconductor device. A given semiconductor device includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions. A gate structure extends in a second direction over the one or more semiconductor regions. A capacitor structure is integrated with one of the source or drain regions of the integrated circuit such that a first electrode of the capacitor contacts the source or drain region and a second electrode of the capacitor contacts a conductive contact formed over the capacitor structure. The capacitor structure may include a ferroelectric capacitor having a ferroelectric layer between the electrodes.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sourav Dutta, Nazila Haratipour, Vachan Kumar, Uygar E. Avci, Shriram Shivaraman, Sou-Chi Chang
  • INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH NIOBIUM BARRIER MATERIALS
    Publication number: 20240112951
    Abstract: Integrated circuit interconnect structures including a niobium-based barrier material. In some embodiments, a layer of essentially niobium may be sputter deposited, for example to a thickness of less than 8 nm at a bottom of an interconnect via. A copper-based fill material may then be deposited over the niobium barrier material. Integrated circuit interconnect metallization may comprise some layers of metallization that have a tantalum-based barrier and other layers of metallization that have a niobium-based barrier.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Philip Yashar, Gokul Malyavanatham, Hema Vijwani
  • SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING
    Publication number: 20240112295
    Abstract: Shared local registers for thread team processing is described. An example of an apparatus includes one or more processors including a graphic processor having multiple processing resources; and memory for storage of data, the graphics processor to allocate a first thread team to a first processing resource, the first thread team including hardware threads to be executed solely by the first processing resource; allocate a shared local register (SLR) space that may be directly reference in the ISA instructions to the first processing resource, the SLR space being accessible to the threads of the thread team and being inaccessible to threads outside of the thread team; and allocate individual register spaces to the thread team, each of the individual register spaces being accessible to a respective thread of the thread team.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Biju George, Fangwen Fu, Supratim Pal, Jorge Parra, Chunhui Mei, Maxim Kazakov, Joydeep Ray
  • HYBRID BONDING TECHNOLOGIES WITH THERMAL EXPANSION COMPENSATION STRUCTURES
    Publication number: 20240113005
    Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Aleksandar Aleksov, Hiroki Tanaka, Brandon Marin, Srinivas Pietambaram, Xavier Brun
  • SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCESSING
    Publication number: 20240111609
    Abstract: Low-latency synchronization utilizing local team barriers for thread team processing is described. An example of an apparatus includes one or more processors including a graphics processor, the graphics processor including a plurality of processing resources; and memory for storage of data including data for graphics processing, wherein the graphics processor is to receive a request for establishment of a local team barrier for a thread team, the thread team being allocated to a first processing resource, the thread team including multiple threads; determine requirements and designated threads for the local team barrier; and establish the local team barrier in a local register of the first processing resource based at least in part on the requirements and designated threads for the local barrier.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Biju George, Supratim Pal, James Valerio, Vasanth Ranganathan, Fangwen Fu, Chunhui Mei
  • SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES
    Publication number: 20240112971
    Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
  • ORDERED THREAD DISPATCH FOR THREAD TEAMS
    Publication number: 20240111590
    Abstract: An apparatus to facilitate ordered thread dispatch for thread teams is disclosed. The apparatus includes one or more processors including a graphic processor, the graphics processor including a plurality of processing resources, and wherein the graphics processor is to: allocate a thread team local identifier (ID) for respective threads of a thread team comprising a plurality of hardware threads that are to be executed solely by a processing resource of the plurality of processing resources; and dispatch the respective threads together into the processing resource, the respective threads having the thread team local ID allocated.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Biju George, Vasanth Ranganathan, Fangwen Fu, Ben Ashbaugh, Roland Schulz
  • AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES
    Publication number: 20240113007
    Abstract: Microelectronic integrated circuit package structures include a first substrate comprising a first bond plane structure on a surface of the first substrate, and a second substrate comprising a second bond plane structure on a surface of the second substrate, where the first and second bond plane structures are in direct physical contact. A conductive trace on the surface of the first substrate is adjacent to a bonding interface between the first and second bond plane structures and over a recessed surface of the first substrate. A first air gap is between the conductive trace and the recessed surface of the first substrate and a second air gap is between the conductive trace and the bonding interface.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Benjamin Duong, Kristof Darmawikarta, Srinivas Pietambaram
  • METHODS AND APPARATUSES FOR THROUGH-GLASS VIAS
    Publication number: 20240112973
    Abstract: Through-glass vias (TGVs) are formed without the use of a planarization step to planarize the TGV fill material after filling holes that extend through a glass layer with the fill material. After the holes are filled with the fill material, the fill material is etched and the glass layer is etched. After etching of the glass is performed, the top and bottom surfaces of the glass layer are recessed relative to the top and bottom surfaces of the fill material in the holes, resulting in formation of fill material stubs. TGV pads are then formed on the fill material stubs. The resulting pads can have protrusions that extend away from a surface of the glass layer. If the TGVs are plated through-holes, a portion of the metal lining the inner wall of a TGV hole can extend past a surface of the glass layer and into a TGV pad.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Gang Duan, Brandon Christian Marin, Suddhasattwa Nad, Srinivas V. Pietambaram
  • POROUS POLYMER DIELECTRIC LAYER ON CORE
    Publication number: 20240113009
    Abstract: An electronic device can include an interposer, a first porous polymer layer, and one or more die. The interposer can include a metallic through via extending from a first surface of the interposer to a second surface of the interposer. The first polymer layer can be adjacent to the first surface of the interposer. The one or more dies can be coupled to the first porous polymer layer and connected to the metallic through via.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Whitney Bryks, Aaditya Candadai, Dilan Seneviratne, Junxin Wang, Peumie Abeyratne Kuragama
  • DYNAMIC APPLICATION PROGRAMMING INTERFACE (API) CONTRACT GENERATION AND CONVERSION THROUGH MICROSERVICE SIDECARS
    Publication number: 20240111615
    Abstract: Embodiments described herein are generally directed to the use of sidecars to perform dynamic API contract generation and conversion. In an example, a first sidecar of a source microservice intercepts a first call to a first API exposed by a destination microservice. The first call makes use of a first API technology specified by a first contract and is originated by the source microservice. An API technology is selected from multiple API technologies. The selected API technology is determined to be different than the first API technology. Based on the first contract, a second contract is dynamically generated that specifies an intermediate API that makes use of the selected API technology. A second sidecar of the destination microservice is caused to generate the intermediate API and connect the intermediate API to the first API.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Marcos Carranza, Cesar Martinez-Spessot, Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Rajesh Poornachandran, Kshitij Arun Doshi
  • 3D OBJECT RECOGNITION USING 3D CONVOLUTIONAL NEURAL NETWORK WITH DEPTH BASED MULTI-SCALE FILTERS
    Publication number: 20240112035
    Abstract: Techniques related to training and implementing convolutional neural networks for object recognition are discussed. Such techniques may include applying, at a first convolutional layer of the convolutional neural network, 3D filters of different spatial sizes to an 3D input image segment to generate multi-scale feature maps such that each feature map has a pathway to fully connected layers of the convolutional neural network, which generate object recognition data corresponding to the 3D input image segment.
    Type: Application
    Filed: December 4, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Ganmei YOU, Zhigang WANG, Dawei WANG
  • MULTICHIP IC DEVICES WITH DIE EMBEDDED IN GLASS SUBSTRATE & A REDISTRIBUTION LAYER INTERCONNECT BRIDGE
    Publication number: 20240113075
    Abstract: Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Brandon Marin, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad
  • TIME-AWARE NETWORK DATA TRANSFER
    Publication number: 20240111691
    Abstract: Techniques for time-aware remote data transfers. A time may be associated with a remote direct memory access (RDMA) operation in a translation protection table (TPT). The RDMA operation may be permitted or restricted based on the time in the TPT.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Daniel Christian Biederman, Kenneth Keels, Renuka Vijay Sapkal, Tony Hurson