Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 10303504
    Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Matthew Fleming, Edwin Verplanke, Andrew Herdrich, Ravishankar Iyer
  • Patent number: 10302324
    Abstract: Methods and apparatus to instruct movement based on sensor data. An example apparatus includes a sensor data receiver to receive sensor data from a sensor device, a preference receiver to receive a user preference, and a preference analyzer to: in response to determining that the sensor data indicates that the user preference is not met at a first location, determine if a second location has a condition that meets the user preference, and in response to determining that the second location has the condition that meets the user preference, transmitting a notification to instruct movement to the second location.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Yoshifumi Nishi, David W. Browning, Mark MacDonald
  • Patent number: 10303609
    Abstract: Embodiments of apparatuses, methods, and systems for independent tuning of multiple hardware prefetchers are described. In an embodiment, an apparatus includes a processor core, a cache memory, a hardware prefetcher, and a prefetch tuner. The hardware prefetcher is to prefetch data for the processor core from a system memory to the cache memory. The prefetch tuner is to adjust a prefetch rate of the hardware prefetcher based on a fraction of late prefetches. The prefetch tuner includes a late prefetch counter to count a number of late prefetches for the hardware prefetcher, a prefetch counter to count a number of prefetches for the hardware prefetcher, and a late prefetch calculator to calculate the fraction of late prefetches based on the number of late prefetches and the number of prefetches.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur
  • Patent number: 10306584
    Abstract: User Equipment (UE), computer readable medium, and method to determine a mobility of the UE are disclosed. The UE may include circuitry configured to determine a plurality of signals from a serving cell. The each signal of the plurality of signals may be one or more of: a reference signal receive power (RSRP), a reference signal receive quality (RSRQ), a received signal strength indicator (RSSI), a signal-to-noise ratio (SNR), a signal-to-interference-ratio (SIR), a signal-to-interference-plus-noise ratio (SINR), and a CQI. The circuitry may be configured to determine a measure for each of a window size of the plurality of signals. Each measure may be a variance of the plurality of signals, a standard deviation of the plurality of signals, a percent confidence interval (CI) of a mean of the measure, and a linear combination of measures. The circuitry may determine whether the UE is stationary based on one or more measures.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Candy Yiu, Ana Lucia Pinheiro, Marta Martinez Tarradell
  • Patent number: 10304686
    Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sasha N. Oster, Fay Hua, Telesphor Kamgaing, Adel A. Elsherbini, Henning Braunisch, Johanna M. Swan
  • Patent number: 10306589
    Abstract: Embodiments of the present disclosure describe systems and methods for hybrid reference signal transmission in wireless communication. In some embodiments, an apparatus may include assignment logic to assign indices to a first set and a second set; identification logic to identify resource elements for a hybrid reference signal in accordance with a first rule for each index in the first set and in accordance with a second rule for each index in the second set, the second rule different from the first rule; and transmission logic to provide the hybrid reference signal for wireless transmission using a common transmission mode in the identified resource elements. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Yang Tang, Jong-Kae Fwu, Yi Hsuan, Seunghee Han
  • Patent number: 10305207
    Abstract: A surface mount connector includes a housing including inner surfaces surrounding a card edge region, and outer surfaces defining an exterior region. The connector also includes a recess in at least one of the outer surfaces, the recess sized to accept a removably engageable arm therein. The connector also defines a cross-sectional width that is smaller in the recess than at a position adjacent to the recess. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Xiang Li, George Vergis
  • Patent number: 10300381
    Abstract: Systems, apparatuses and methods may leverage technology that identifies sensor data, automatically determines a change in an affective state of one or more individuals based at least in part on the sensor data and conducts an update to a game score based on the change in the affective state. In one example, the game score is associated with a player and the one or more individuals are individuals other than the player.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jennifer A. Healey, Lama Lachman, Rita H. Wouhaybi, Giuseppe Raffa
  • Patent number: 10304804
    Abstract: Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside. In certain embodiments, the passive device is formed on a self-assembled monolayer (SAM). Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Fay Hua, Telesphor Kamgaing, Johanna M. Swan
  • Patent number: 10301719
    Abstract: A method of forming a low-dielectric-constant amorphous hydrogenated boron carbide film on a substrate includes positioning the substrate within a plasma enhanced chemical vapor deposition (PECVD) chamber, providing a boron carbide precursor and introducing the boron carbide precursor into a carrier gas to form a carrier gas-precursor mixture. The method also includes introducing the carrier gas-precursor mixture into the PECVD chamber. The method also includes applying radio frequency power within the PECVD chamber to the carrier gas-precursor mixture to form one or more plasmas containing one or more species containing at least one of boron, carbon or hydrogen. The method also includes forming the low-dielectric-constant amorphous hydrogenated boron carbide film on the substrate within the PECVD chamber.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 28, 2019
    Assignees: The Curators of the University of Missouri, Intel Corporation
    Inventors: Michelle Paquette, Bradley Nordell, Anthony N. Caruso, Sean King
  • Patent number: 10299716
    Abstract: Apparatus, systems, and/or methods may provide a mental state determination. For example, a data collector may collect image data for a side of a face of a user from an image capture device on the user (e.g., a wearable device). The image data may include two or more perspectives of a feature on the side of the face of the user. In addition, a state determiner may determine a mental state of the user based on the image data. In one example, fields of view may be combined to determine a total region and/or a total overlap region. Changing the position that one or more image capture devices point may modulate the total region and/or the total overlap region. In addition, one or more sensors may be utilized to further improve mental data determinations.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Cagri Tanriover, Sinem Aslan, Nese Alyuz Civitci, Ece Oktay, Eda Okur, Asli Arslan Esme
  • Patent number: 10303834
    Abstract: An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to supply to the region that enables the region to operate at a target speed. The control circuit also receives a first criticality value of a first path of a design programmed in the region. The first criticality value is based on a first propagation time of the first path and a first allowable time to traverse the first path while enabling the region to operate at the target speed. The control circuit further instructs a power regulator to supply voltage to the region based at least in part on the target voltage value and the first criticality value. The integrated circuit also includes the power regulator communicatively coupled to the at least one region. The power regulator supplies power to the at least one region.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: David Michael Lewis, Herman Henry Schmit
  • Patent number: 10304927
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10303503
    Abstract: An apparatus and method for hardware protection of a virtual machine monitor (VMM) runtime integrity watcher is described. A set of one or more hardware range registers that protect a contiguous memory space that is to store the VMM runtime integrity watcher. The set of hardware range registers are to protect the VMM runtime integrity watcher from being modified when loaded into the contiguous memory space. The VMM runtime integrity watcher, when executed, performs an integrity check on a VMM during runtime of the VMM.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Shamanna M. Datta, Alberto J. Munoz, Mahesh S. Natu, Scott T. Durrant
  • Patent number: 10304929
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Patent number: 10303525
    Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Christopher J. Hughes, Robert Valentine, Milind B. Girkar, Hideki Ido, Youfeng Wu, Cheng Wang
  • Patent number: 10306509
    Abstract: In embodiments, apparatuses, methods, and storage media may be described for identifying subframes in a radio frame on which a UE may receive a Physical Downlink Control Channel (PDCCH) or enhanced PDCCH (ePDCCH) transmission. Specifically, the UE may receive multiple indications of uplink/downlink (UL/DL) subframe configurations and identify one or more subframes in which the UE may receive the PDCCH or ePDCCH transmission. The UE may then monitor one or more of the identified subframes and base discontinuous reception (DRX) timer functionality on one or more of the identified subframes.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Hong He, Youn Hyoung Heo, Mo-Han Fong, Alexey Khoryaev
  • Patent number: 10303594
    Abstract: An apparatus to facilitate guaranteed forward progress for graphics data is disclosed. The apparatus includes a plurality of ports to receive and transmit streams of graphics data, one or more buffers associated with each of the plurality of ports to store the graphics data and switching logic to virtually partition each of the one or more buffers to allocate a dedicated buffer to receive each of a plurality of independent streams of graphics data.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Joydeep Ray, Niranjan L. Cooray, Abhishek R. Appu
  • Patent number: 10305570
    Abstract: For example, a wireless station may be configured to modulate a plurality of data bit sequences into a plurality of constellation points in first and second spatial streams according to a DCM, a data bit sequence of the plurality of data bit sequences includes a sequence of a plurality of data bits, modulating the plurality of data bit sequences includes modulating the sequence of the plurality of data bits into a first constellation point in the first spatial stream and a second constellation point in the second spatial stream, the second constellation point is a complex conjugate of the first constellation point; and to transmit an OFDM transmission over a wireless communication channel in a frequency band above 45 GHz, the OFDM transmission based on the plurality of constellation points in the first and second spatial streams.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Artyom Lomayev, Alexander Maltsev, Michael Genossar, Carlos Cordeiro
  • Patent number: 10303606
    Abstract: Technologies for migration of dynamic home tile mapping are described. A cache controller can receive coherence messages from other processor cores on the die. The cache controller records locations from which the coherence messages originate and determine distances between the requested home tiles and the locations from which the coherence messages originate. The cache controller determines whether an average distance between a particular home tile, whose identifier is stored in the home tile table, exceeds a threshold. When the average distance exceeds the defined threshold, the cache controller migrates the particular home tile to another location.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Daehyun Kim, Jong Soo Park, Richard M. Yoo
  • Patent number: 10305703
    Abstract: The presently-disclosed solution enables continuous time linear equalizer (CTLE) tuning without needing to perform bit error rate (BER) measurements. Because time consuming BER measurements are avoided, the CTLE tuning may be performed more rapidly as to reduce substantially the time required for link training. Furthermore, this solution re-uses decision feedback equalizer (DFE) adaptation circuitry so as to be highly efficient in its implementation. One embodiment relates to a method that tunes the CTLE based on results from the adaptation of the tap values of the DFE. Another embodiment relates to an apparatus that includes an interface for a control module to control a setting of a CTLE and an adaptation engine for a DFE. The value for the setting of the CTLE is selected using the adapted tap 1 value of the DFE as a figure of merit. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel corporation
    Inventors: Onkar Patki, Kenneth Taylor, Nigel Gulstone
  • Patent number: 10303612
    Abstract: Apparatuses, systems, and methods for hardware-level data encryption having integrity and replay protection are described. An example electronic device includes a memory encryption engine (MEE) having a MEE cache configured to store a plurality of MEE cache lines, each MEE cache line comprising a plurality of cryptographic metadata blocks, where each metadata block is associated with each of a plurality of encrypted data lines stored in a memory, and each MEE cache line includes a bit vector mapped to the plurality of metadata blocks, where a set bit in the bit vector indicates that the associated metadata block has been accessed by one or more processors, and MEE circuitry configured to select a replacement candidate from the plurality of MEE cache lines for eviction from the MEE cache based on a number of accessed metadata blocks in the replacement candidate as indicated by the associated bit vector.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Siddhartha Chhabra
  • Patent number: 10305974
    Abstract: One embodiment provides an apparatus. The apparatus includes ranker logic. The ranker logic is to rank each of a plurality of compute nodes in a data center based, at least in part, on a respective node score. Each node score is determined based, at least in part, on a utilization (U), a saturation parameter (S) and a capacity factor (Ci). The capacity factor is determined based, at least in part, on a sold capacity (Cs) related to the compute node. The ranker logic is further to select one compute node with a highest node score for placement of a received workload.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Alexander Leckey, Joseph M. Butler, Thijs Metsch, Giovani Estrada, Vincenzo M. Riccobene, John M. Kennedy
  • Patent number: 10303620
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 10305976
    Abstract: A method for managing computing includes replicating a subset of a machine state of a first computing device onto a second computing device, wherein the subset of the machine state is required to execute machine code. Execution of the machine code is offloaded to the second computing device.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Chit Kwan Lin, Arnab Paul, Gautham N. Chinya
  • Patent number: 10303225
    Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Zhichao Zhang, Cemil Geyik, Guneet Kaur
  • Patent number: 10306460
    Abstract: Some demonstrative embodiments include devices, systems and/or methods to establish a connection to the Internet via a local gateway (L-GW) function for a LIPA or a SIPTO@LN. The establishment of the connection to the Internet may be performed, for example, by at least one of an E-RAB SETUP procedure, an INITIAL CONTEXT SETUP procedure, an INITIAL UE MESSAGE procedure or an UPLINK NAS TRANSPORT procedure.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Alexander Sirotkin, Alexandre S. Stojanovski
  • Patent number: 10303471
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Mostafa Hagog, Robert Valentine, Amit Gradstein, Simon Rubanovich, Zeev Sperber
  • Patent number: 10304799
    Abstract: BGA packages with a LGA package extension. First lands on a substrate are populated with solder balls, while only solder paste is dispensed on second lands that are surrounded by the first lands. Differences in solder stand-off may accommodate non-planarity in a package or the insertion of an LGA extension component, such as an IC or one or more discrete devices. Where an LGA extension component is attached to the second lands, solder paste may be further dispensed on third lands located on a package-side of the extension component. A BGA package is then attached to the first lands and third lands. The larger volume BGA solder connections maintaining mechanical reliability, particularly where the solder ball interconnects form a perimeter surrounding the low-volume solder interconnects.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Tyler Leuten, Min-Tih Lai
  • Patent number: 10303477
    Abstract: A processor includes at least one memory controller, and a decode unit to decode a persistent commit demarcate instruction. The persistent commit demarcate instruction is to indicate a destination storage location. The processor also includes an execution unit coupled with the decode unit and the at least one memory controller. The execution unit, in response to the persistent commit demarcate instruction, is to store a demarcation value in the destination storage location. The demarcation value may demarcate at least all first store to persistent memory operations that are to have been accepted to memory when the persistent commit demarcate instruction is performed, but which are not necessarily to have been stored persistently, from at least all second store to persistent memory operations that are not yet to have been accepted to memory when the persistent commit demarcate instruction is performed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Kshitij A. Doshi
  • Patent number: 10306543
    Abstract: Embodiments of a method and apparatus for discovery and association, by a mobile station, of a femto base station from a plurality of base stations. The mobile station may select a base station for consideration for association by decoding a physical layer identifier to determine that the base station is a macro base station and select a different base station based on other considerations. Other embodiments may be described and claimed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Sassan Ahmadi, Shahrnaz Azizi
  • Patent number: 10304940
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10306420
    Abstract: Embodiments of self-locating computing devices, systems, and methods are described. In some embodiments, a computing device may include a Wireless Credential Exchange Module (WCEM) to detect one or more location tags and a management engine, coupled to the WCEM, to retrieve information of the one or more location tags from the WCEM, and to provide an asset management server with an identifier of the computing device and the information of the one or more location tags or location information of the computing device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Shen Zhou, Zhijie Sheng, Thanunathan Rangarajan, Junjie Huang
  • Patent number: 10303953
    Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mayuresh M. Varerkar, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Sherine Abdelhak, Sachin Godse, Farshad Akhbari, Narayan Srinivasa, Altug Koker, Nadathur Rajagopalan Satish, Dukhwan Kim, Feng Chen, Abhishek R. Appu, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 10306673
    Abstract: A front-end unit that operates within a C-RAN architecture to perform the functions of cellular signal processing and resource selection between an RRU and the BBU pool network is described. The front-end unit supports flexible load migration and CoMP (coordinated multipoint) in the CRAN BBU while also reducing data transmission within the BBU pool network or between the BBU pool network and the RRU.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Zhiyuan Zhang, Qianying Zhu, Xinxin Zhang, Shunyu Zhu, Xiangbin Wu, Xuebin Yang, Senjie Zhang, Guangjie Li, Xu Zhang
  • Patent number: 10304213
    Abstract: An apparatus for a near lossless compression scheme is described herein. The apparatus includes an image processing pipeline and a compressor. The image processing pipeline is to apply a plurality of processing stages to high dynamic range images to output a plurality of intermediate processed images, wherein each image comprises a plurality of pixel components. The compressor is to generate compression tiles of the plurality of intermediate processed images, wherein each output of the plurality of processing stages is compressed independently of the other processing stage.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Rakefet Kol, Rony Zatzarinni, Hadas Dahan, Pavel Kounitsky
  • Patent number: 10306690
    Abstract: Embodiments include apparatuses, methods, and systems including a communication device having a first transceiver to communicate with a first device through a first communication link, and a second transceiver to communicate with a second device through a second communication link. In addition, there may be a third communication link between the first device and the second device. For the communication device, the second transceiver may consume less power for the second communication link than a power the first transceiver consumes to communicate through the first communication link. The communication device may communicate a traffic with the first device via the second device, through the second and third communication links, using the second transceiver. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Jinshi Huang
  • Patent number: 10306550
    Abstract: Some demonstrative embodiments include devices, systems and methods of Wireless Local Area Network (WLAN) setting of a User Equipment (UE). For example, a UE may include a Wireless Local Area Network (WLAN) transceiver to communicate with a WLAN; a cellular transceiver to communicate with a cellular network; a user interface to provide a user with a plurality of WLAN setting options and to receive an indication of a selected WLAN setting from the plurality of WLAN setting options; and a connection manager to cause the WLAN transceiver to operate according to the selected WLAN setting.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 28, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Alexander Sirotkin, Sudeep Divakaran, Anand Muralidharan
  • Patent number: 10306700
    Abstract: A disclosed example method to setup a Groupcast with Retries service for use with wireless communications involves sending an association response from an access point to a wireless station, the association response being responsive to a General Link capability of the wireless station received in an association request at the access point from the wireless station; and operating the access point to concurrently establish a General Link and the Groupcast with Retries service between the access point and the wireless station based on the association request indicating that the wireless station supports the Groupcast with Retries service.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventor: Ganesh Venkatesan
  • Patent number: 10303899
    Abstract: A host Virtual Machine Monitor (VMM) operates “blindly,” without the host VMM having the ability to access data within a guest virtual machine (VM) or the ability to access directly control structures that control execution flow of the guest VM. Guest VMs execute within a protected region of memory (called a key domain) that even the host VMM cannot access. Virtualization data structures that pertain to the execution state (e.g., a Virtual Machine Control Structure (VMCS)) and memory mappings (e.g., Extended Page Tables (EPTs)) of the guest VM are also located in the protected memory region and are also encrypted with the key domain key. The host VMM and other guest VMs, which do not possess the key domain key for other key domains, cannot directly modify these control structures nor access the protected memory region. The host VMM, however, can verify correctness of the control structures of guest VMs.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: David M. Durham, Gilbert Neiger, Barry E. Huntley, Ravi L. Sahita, Baiju V. Patel
  • Patent number: 10303900
    Abstract: Technologies for secure programming of a cryptographic engine include a computing device with a cryptographic engine and one or more I/O controllers. The computing device establishes, an invoking secure enclave using secure enclave support of a processor. The invoking enclave configures channel programming information, including a channel key, and invokes a processor instruction with the channel programming information as a parameter. The processor generates wrapped programming information including an encrypted channel key and a message authentication code. The encrypted channel key is protected with a key known only to the processor. The invoking enclave provides the wrapped programming information to untrusted software, which invokes a processor instruction with the wrapped programming information as a parameter. The processor unwraps and verifies the wrapped programming information and then programs the cryptographic engine.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Gideon Gerzon, Reshma Lal, Bin Xing, Pradeep M. Pappachan, Steven B. McGowan
  • Patent number: 10303902
    Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Hema C. Nalluri, Aditya Navale, Murali Ramadoss
  • Patent number: 10304418
    Abstract: An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Daniel Greenspan, Randy Osborne, Zvika Greenfield, Israel Diamand, Asaf Rubinstein
  • Patent number: 10304421
    Abstract: An apparatus and method are described for efficiently rendering an transmitting to a remote display.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Jason Tanner, Joydeep Ray, Altug Koker, Abhishek R. Appu, Pattabhiraman K
  • Patent number: 10304556
    Abstract: An example system that includes a processor, a memory controller, a memory, and a memory device. The memory controller coupled to the processor. The memory coupled to the memory controller, the memory to store a first copy of data stored according to a first test data pattern for use by a memory scrubbing operation. The memory device coupled to the memory controller. The memory controller may mirror a first set of data stored in a first block of memory of the memory device to a second block of memory of the memory device. The memory controller may also write the first copy of data to the first block of memory as a second copy of data. The memory controller send a first message to the processor indicating a memory fault error for the first block of memory.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Anthony E. Luck
  • Patent number: 10304510
    Abstract: Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as spin transfer torque (STT) memory is to be followed by a write operation to the location. Additionally, a current level associated with the read operation may be increased, wherein the read operation is conducted from the location at the increased current level. The increased current level may cause a reset of all bits in the location.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Helia A. Naeimi
  • Patent number: 10304946
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
  • Patent number: 10304235
    Abstract: An apparatus and method are described for volumetric integration. For example, one embodiment of a graphics processing apparatus comprises: single instruction multiple data (SIMD) hardware to perform graphics processing operations; ray segmentation circuitry to sub-divide a ray traversing a volumetric object into N segments; and segment-based volumetric integration circuitry for performing volumetric integration over the N segments in parallel using the single-instruction multiple data (SIMD) hardware.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventor: Ingo Wald
  • Patent number: 10305019
    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Shawna M. Liff
  • Patent number: 10302367
    Abstract: A non-metallic vapor chamber includes a composite wick structure that fills a non-metallic housing. The composite wick structure provides mechanical strength and structural rigidity to the non-metallic vapor chamber. The composite wick structure includes a first hydrophilic wick portion and a second hydrophobic wick portion. A condensed working fluid flows through the first hydrophilic wick portion from a condensation region to a region proximate one or more thermal energy producing devices. A vaporized working fluid flows through the second hydrophobic wick portion from the region proximate one or more thermal energy producing devices to a condensation region where the vaporized working fluid is condensed for reuse.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Mark MacDonald