Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.

Abstract: For example, an apparatus may be configured to generate, transmit, receive and/or process a frame including a multiple Basic Service Set Identifier (BSSID) element corresponding to a multiple BSSID set including a reporting AP, the BSSID element including one or more non-transmitted BSSID profile elements corresponding to one or more other APs belonging to the multiple BSSID set, wherein a non-transmitted BSSID profile element corresponding to an other AP includes one or more elements of information corresponding to the other AP, and a multi-link element, the multi-link element including one or more profile subelements for one or more reported APs of an other MLD including the other AP, respectively, wherein a profile subelement corresponding to a reported AP includes one or more elements of information corresponding to the reported AP.

Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

Abstract: This disclosure describes systems, methods, and devices related to extremely high throughput (EHT) resource unit (RU) allocation. A device may utilize a tone plan to generate an EHT frame to be sent using an 80 MHz frequency band, wherein the tone plan comprises a plurality of null tones. The device may encode one or more resource units (RUs) for the EHT frame, wherein the one or more RUs comprise at least one of a 26-tone RU, a 52-tone RU, a 106-tone RU, a 242-tone RU, a 484-tone RU, or a 996-tone RU, wherein the 106-tone RU, the 242-tone RU, and the 484-tone RU comprise null tones located at least at subcarriers ±258, ±257, ±256, ±255, and ±254. The device may cause to send the EHT frame to a first station device using the 80 MHz frequency band.

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

Abstract: An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.

Abstract: Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

Abstract: Described are precursor compounds and methods for atomic layer deposition of films containing scandium(III) oxide or scandium(III) sulfide. Such films may be utilized as dielectric layers in semiconductor manufacturing processes, particular for depositing dielectric films and the use of such films in various electronic devices.

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

Abstract: Techniques for a vapor chamber with less dead space are disclosed. In an illustrative embodiment, a vapor chamber is formed by folding a sheet and sealing the edges. The edges seal the vapor chamber but take up a relatively large amount of space without allowing for vapor to be transported in that space. The folded edge takes up less space, reducing the overall footprint of the vapor chamber. The vapor chamber with a smaller footprint can allow for, e.g., more space for motherboard area, more space for a battery, and/or a smaller form factor overall.

Abstract: Technologies for pluggable optical connectors are disclosed. In the illustrative embodiment, an optical plug includes a ferrule with one or more optical fibers. The optical plug also includes a ferrule holder that holds the ferrule and a housing that encloses the ferrule and ferrule holder. The ferrule holder can move relative to the house, and the ferrule can move relative to the ferrule holder and the housing. As the optical plug is plugged into a socket, alignment features in the housing coarsely align the ferrule. Intermediate alignment features in the ferrule holder then engage, aligning the ferrule more precisely. As the optical plug is fully plugged in, fine alignment features in the ferrule engage, precisely aligning the ferrule and the optical fibers with the optical socket.

Abstract: Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Abstract: Techniques for improving exception-based invocation of instrumentation handler programs include executing, by a processor, an interrupt instruction of an instrumented program, the interrupt instruction having an interrupt number; searching for the interrupt number in an interrupt table; and in response to the interrupt number being found in the interrupt table, saving an address of a next instruction of the instrumented program after the interrupt instruction as a return address, determining a destination address, in an interrupt destination table, of a beginning of an instrumentation handler program associated with the interrupt number and transferring control of the instrumented program to the instrumentation handler program at the destination address.

Abstract: This disclosure describes systems, methods, and devices related to enhanced L-SIG. A device may generate a frame for 60 gigahertz (GHz) transmission, the frame comprising one or more fields to carry information associated with one or more station devices (STAs). The device may generate a special legacy signal (L-SIG) field comprising one or more subfields for operation in the 60 gigahertz (GHz) transmission. The device may include the L-SIG field in the frame. The device may cause to send the frame to the one or more STAs.

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein.

Abstract: A circuit system includes a support device having an interconnection conductor. The circuit system also includes first, second, and third integrated circuits that are mounted on the support device. The interconnection conductor couples the first integrated circuit to the third integrated circuit. The second integrated circuit is between the first integrated circuit and the third integrated circuit.

Abstract: Technologies for untrusted code execution include a computing device having a processor with sandbox support. The computing device executes code included in a native domain in a non-privileged, native processor mode. The computing device may invoke a sandbox jump processor instruction during execution of the code in the native domain to enter a sandbox domain. The computing device executes code in the sandbox domain in a non-privileged, sandbox processor mode in response to invoking the sandbox jump instruction. While executing in the sandbox processor mode, the processor denies access to memory outside of the sandbox domain and may deny execution of one or more prohibited instructions. From the sandbox domain, the computing device may execute a sandbox exit instruction to exit the sandbox domain and resume execution in the native domain. The computing device may execute processor instructions to configure the sandbox domain. Other embodiments are described and claimed.

Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

Abstract: There is disclosed a system, including apparatus, methods and computer programs, for running native software applications (apps) and HTML5 web-based apps on a computing device, particularly a mobile computing device, in a multitasking mode of operation. In one embodiment, touch screen displays having one or more browsers are adapted to run one or more HTML5 apps, and receive input from hand gestures. One or more software modules execute on the operating system and are responsive to a dragging gesture applied to an HTML5 app displayed in a full screen mode, to subdivide the screen display and display the HTML5 app in one of the subdivided areas and display icons used to launch a second HTML5 app in a different one of the subdivided areas. The second HTML5 app is run concurrently with the first HTML5 app in order to provide multi-tasking between the first and second apps.

Abstract: Embodiments are directed to a composite binary decomposition network. An embodiment of a computer-readable storage medium includes executable computer program instructions for transforming a pre-trained first neural network into a binary neural network by processing layers of the first neural network in a composite binary decomposition process, where the first neural network having floating point values representing weights of various layers of the first neural network. The composite binary decomposition process includes a composite operation to expand real matrices or tensors into a plurality of binary matrices or tensors, and a decompose operation to decompose one or more binary matrices or tensors of the plurality of binary matrices or tensors into multiple lower rank binary matrices or tensors.

Abstract: Examples described herein relate to an offload processor to receive data for transmission using a network interface or received in a packet by a network interface. In some examples, the offload processor can include a packet storage controller to determine whether to store data in a buffer of the offload processing device or a system memory after processing by the offload processing device. In some examples, determine whether to store data in a buffer of the offload processor or a system memory is based on one or more of: available buffer space, latency limit associated with the data, priority associated with the data, or available bandwidth through an interface between the buffer and the system memory. In some examples, the offload processor is to receive a descriptor and specify a storage location of data in the descriptor, wherein the storage location is within the buffer or the system memory.

Abstract: A method, device, and system for conducting trusted payment transactions including establishing a trust relationship between a first mobile computing device and a second mobile computing device. The first mobile computing device may initiate a payment transaction with a point-of-sale device, communicate with the second mobile communication device to retrieve payment information from the second mobile communication device, and complete the payment transaction with the point-of-sale device using the payment information. The second mobile computing device is configured to verify the user and identity of the first mobile computing device prior to providing the payment information. Communications between the mobile computing devices may be encrypted using pre-determined encryption techniques.

Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.

Abstract: A processor to facilitate execution of a single-precision floating point operation on an operand is disclosed. The processor includes one or more execution units, each having a plurality of floating point units to execute one or more instructions to perform the single-precision floating point operation on the operand, including performing a floating point operation on an exponent component of the operand; and performing a floating point operation on a mantissa component of the operand, comprising dividing the mantissa component into a first sub-component and a second sub-component, determining a result of the floating point operation for the first sub-component and determining a result of the floating point operation for the second sub-component, and returning a result of the floating point operation.

Abstract: Systems, apparatuses and methods may provide for developer stage technology that embeds binary code into an application binary file, wherein the binary code corresponds to vector functions and non-vector functions in statically typed source code, and generates intermediate representation (IR) data, wherein the intermediate representation data corresponds to the vector functions in the statically typed source code. Additionally, the developer stage technology embeds the IR data in the application binary file. Moreover, deployment stage technology may generate a first compilation output based on the application binary file and detect a capability change in an execution environment associated with the first compilation output. The deployment stage technology may also generate, in response to the detected capability change, a second compilation output based on the first compilation output.

Abstract: Disclosed herein are integrated circuit (IC) package lids with polymer features, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A foot or rib of the lid may include a polymer material.

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: Methods, apparatuses, and computer readable media for a common preamble for wireless local-area networks (WLANs). An apparatus of an access point (AP) or station (STA) comprising processing circuitry configured to encode an AP trigger frame that includes a resource allocation for other APs to transmit trigger frames to perform an uplink or downlink multi-user transmission with stations (STAs). The resource allocation includes information so that the transmissions are coordinated at the physical level to lessen interference among the APs and the stations. The processing is configured to encode a trigger frame for multi-AP request-to-send (RTS), the multi-AP trigger frame comprising for each of a plurality of APs, the trigger frame indicating that each of a plurality of APs are to transmit a physical (PHY) protocol data unit (PPDU) comprising a request-to-send (RTS) or multi-user (MU) RTS (MU-RTS).

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Abstract: An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: A sample and hold scheme for temperature measurements for non-volatile memory can enable significant reduction in temperature readout latency. In one example thermometer circuits are enabled at a refresh rate to cause the temperature to be sensed and latched at regular intervals. By performing the temperature readings in the background at a refresh rate instead of on-demand, the temperature is available to service commands with almost no latency.

Abstract: Various systems and methods of establishing and utilizing device management (DM) services in Internet of Things (IoT) networks and similar distributed network architectures, are described. In an example, RESTful messaging within IoT operational and resource models are used to establish, instantiate, and operate DM services having various roles within an IoT framework abstraction.

Abstract: Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

Abstract: Technologies for providing secure utilization of tenant keys include a compute device. The compute device includes circuitry configured to obtain a tenant key. The circuitry is also configured to receive encrypted data associated with a tenant. The encrypted data defines an encrypted image that is executable by the compute device to perform a workload on behalf of the tenant in a virtualized environment. Further, the circuitry is configured to utilize the tenant key to decrypt the encrypted data and execute the workload without exposing the tenant key to a memory that is accessible to another workload associated with another tenant.

Abstract: Performing a synchronization to allow a second wireless communication circuit of a wireless device operating in a second wireless communication network to operatively coexist with a first wireless communication network of the wireless device operating in a first wireless communication network in one or more wireless communication channels according to a time division multiplexing (TDM), wherein the method includes determining whether the one or more wireless communication channels are busy comprising determining whether a packet has been detected by the wireless device in the one or more wireless communication channels and/or determining whether the wireless device has sensed energy in the one or more wireless communication channels when one or more back-off counters associated TDM plan is zero; and granting to the second communication network, in response to determining the one or more wireless communication channels are busy, use of the one or more wireless communication channels.

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.