Abstract: An audio processing device and method uses audio signals from a virtual rotating microphone for acoustic angle of arrival detection using a doppler effect technique.

Abstract: This disclosure describes systems, methods, and devices related to long range beacon. A device may determine one or more co-located frequency bands with a 6 GHz access point (AP). The device may generate a reduced neighbor report (RNR), wherein the RNR comprises information associated with the 6 GHz AP. The device may determine a minimum bandwidth to transmit a beacon frame using a communication mode. The device may cause to send the beacon frame to a first station device.

Abstract: An apparatus is described. The electronic circuit board having electronic components thereon. A protective material coated on an exposed material of the electronic circuit board and the electronic components. The protective material being chemically inert with the exposed material. The protective material being chemically inert with an immersion bath cooling liquid that the electronic circuit board and the electronic components are to be immersed within. A thermal cooling structure of one of the electronic components that is designed to transfer heat into the immersion bath cooling liquid is not coated with the protective material.

Abstract: Disclosed embodiments are relate to heat transfer devices or heat exchangers for computing systems, and in particular, to heat pipes for improved thermal performance at a cold plate interface. A thermal exchange assembly includes a heat pipe (HP) directly coupled to a cold plate. The HP includes a window, which is a recessed or depressed portion of the HP. The window is attached to the cold plate at a window section of the cold plate. The cold plate is configured to be placed on a semiconductor device that generates heat during operation. The cold plate transfers the heat to the HP with less thermal resistance than existing HP solutions. Other embodiments may be described and/or claimed.

Abstract: Techniques for storage and processing for distributed file systems are disclosed. In the illustrative embodiment, padding is placed between data elements in a file to be stored on a distributed file system. The file is to be split into several objects in order to be stored in the distributed file system, and the padding is used to prevent a data element from being split across two different objects. The objects are stored on data nodes, which analyze the objects to determine which data elements are present in the object as well at the location of those objects. The location of the objects is saved on the data storage device, and those locations can be used to perform queries on the data elements in the object on the data storage device itself. Such an approach can reduce transfer of data elements from data storage to local memory of the data node.

Abstract: Techniques are disclosed for performing RFID motion tracking in an intelligent manner that facilitates the generation of accurate and useful metrics for marketing and other applications. The techniques function to reduce problematic false positive rates on RFID tags attached to items to improve the accuracy of the motion presence of a small subset of browsed items among a much larger set of tagged items in the same space. This accurate motion inference enables the calculation of metrics such as customer-item interaction duration, pauses in interactions (potentially indicating close examining), and the extraction of patterns of motion that can indicate interest leading to realized sales, as well as concurrent motion detection of multiple items indicating which related items shall be placed in close proximity to increase sales of matching items.

Abstract: Disclosed herein are diamondoid materials in quantum computing devices, as well as related methods, devices, and materials. For example, in some embodiments, a quantum computing device may include: qubit circuitry, an interconnect in conductive contact with the qubit circuitry, and a dielectric material proximate to the interconnect, wherein the dielectric material includes a diamondoid film.

Abstract: A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.

Abstract: IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a source or drain (S/D) region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact structure, and a liner material on at least a portion of a sidewall of the gap, the liner material comprising aluminum and oxygen.

Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

Abstract: Described herein is a technique in which a plurality of distortion meshes compensate for radial and chromatic aberrations created by optical lenses. The plurality of distortion meshes may include different lens specific parameters that allow the distortion meshes to compensate for chromatic aberrations created within received images. The plurality of distortion meshes may correspond to a red color channel, green color channel, or blue color channel to compensate for the chromatic aberrations. The distortion meshes may also include shaped distortions and grids to compensate for radial distortions, such as pin cushion distortions. In one example, the system uses a barrel-shaped distortion and a triangulation grid to compensate for the distortions created when the received image is displayed on a lens.

Abstract: An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to interface circuitry to obtain a pre-trained detection model, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to tune the pre-trained detection model based on first local behavior data and execute the tuned detection model to detect an anomaly in second local behavior data associated with the apparatus.

Abstract: A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped dielectric material is performed, providing well-aligned metal layers in the region of the bridge die and the region around the bridge die.

Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.

Abstract: Key-value (KV) caching accelerates inference in large language models (LLMs) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. Due to large context lengths in modern LLMs, KV cache size can exceed the model size, which can negatively impact throughput. To address this issue, a multi-granular clustering-based solution for KV cache compression can be implemented. Key tensors and value tensors corresponding unimportant tokens can be approximated using clusters created at different clustering-levels with varying accuracy. Accuracy loss can be mitigated by using proxies produced at finer granularity clustering-level for a subset of attention heads that are more significant. More significant attention heads can have a higher impact on model accuracy than less significant attention heads. Latency is improved by retrieving proxies from a faster memory for a subset of attention heads that are less significant, when impact on accuracy is lower.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Abstract: The technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ECC) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive OR (XOR) operation on the plurality of ECC bits and a fixed encoding pattern to generate a plurality of encoded ECC bits and store the data and the plurality of encoded ECC bits in the memory.

Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

Abstract: IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a S/D region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact structure, and a liner material over at least a portion of a sidewall of the region below the contact structure, the liner material comprising aluminum and oxygen.

Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

Abstract: Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, a radar system may include a plurality of radar devices. For example, a radar device may include one or more Transmit (Tx) antennas to transmit radar Tx signals, one or more Receive (Rx) antennas to receive radar Rx signals, and a processor to generate radar information based on the radar Rx signals. In one example, the radar system may be implemented as part of a vehicle. In other aspects, the radar system may include any other additional or alternative elements and/or may be implemented as part of any other device or system.

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.

Abstract: Microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. In one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second face, or the sidewall and extends from the surface into the glass core by a total depth of up to about 50 micron, the bulk region is a portion of the glass core further away from the surface than the surface region, and a density of the surface region is higher than a density of the bulk region, e.g., at least about 5% higher or at least about 7.5% higher.

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: A processing unit, comprising a display interface to control a foldable display with multiple segments created by fold lines in the foldable display. The processing unit also including a plurality of lanes to connect the display interface to the foldable display, where each segment of the foldable display is connected to a lane. The processing unit also including a multi-segment protocol component to instruct the display interface to drive data to each segment of the display through the plurality of lanes.

Abstract: According to various aspects, controller for an automated machine may include: a processor configured to: compare information about a function of the automated machine with information of a set of tasks available to a plurality of automated machines; negotiate, with the other automated machines of the plurality of automated machines and based on a result of the comparison, which task of the set of tasks is allocated to the automated machine.

Abstract: In one embodiment, a device comprises interface circuitry and processing circuitry. The processing circuitry receives, via the interface circuitry, a video stream captured by a camera during performance of an industrial process, wherein the video stream comprises a sequence of frames; detects, based on analyzing the sequence of frames, a degree of particle scatter that occurs during performance of the industrial process; and determines, based on the degree of particle scatter, that an anomaly occurs during performance of the industrial process.

Abstract: Examples described herein relate to programming a memory rule for a home agent, wherein the programming a memory rule for a home agent comprises: receiving at least one memory rule programming and based on a cluster associated with the home agent, configuring a memory rule register using a memory rule programming from among the at least one memory rule programming. In some examples, receiving at least one memory rule programming includes receiving a first memory rule programming and receiving a second memory rule programming. In some examples, a mask is applied to reject the first memory rule programming; and applying the mask to accept the second memory rule programming and program the memory rule for the home agent.

Abstract: Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

Abstract: Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory.

Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described.

Abstract: There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

Abstract: Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. The aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.

Abstract: A hybrid resonator includes an acoustic wave resonator (AWR) having a piezoelectric material; a first electrical contact, electrically conductively connected to the piezoelectric material; and a second electrical contact, electrically conductively connected to the piezoelectric material. The hybrid resonator further includes a first resonant circuit, electrically conductively connected in series or parallel to the acoustic wave resonator via at least one of the first electrical contact and the second electrical contact.

Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

Abstract: An optical system can include a optical receiver comprising an optical waveguide, an optical lid adjacent the waveguide, and a reflective surface proximate an output of the optical waveguide to direct light from the waveguide towards an output of the optical lid. The optical system can also include a photodetector (PD) die comprising a substrate, a concave mirror, and a photodetector. The concave mirror is formed on a first side of the substrate and the photodetector is disposed on a second side of the substrate, the first side opposite the second side, wherein the photodetector is disposed on the second side of the PD die offset from the optical axis of the optical element.

Abstract: Embodiments include a method of opening a Quick User Datagram Protocol (UDP) Internet Connections (QUIC) socket on a computing platform, initializing QUIC packet processing of a hardware-based offloader, opening a QUIC connection to the offloader, and transmitting a first QUIC packet to the offloader over the QUIC connection. The hardware-based offloader encrypts and transmits the QUIC packet.

Abstract: A component (e.g. a module configuration system) of a device may include an interface and processor circuitry. The processor circuitry may be configured to: determine identification information of a hardware device (e.g. module, microchip) connected to the component via the interface; obtain device information for the connected hardware device based on the determined identification information; and initialize the connected hardware device based on the obtained device information.

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, a compute die over the package substrate, and an optics die over the package substrate. In an embodiment, the optics die comprises grating couplers. In an embodiment, an optical connector for optically coupling optical fibers to the grating couplers is provided. In an embodiment, the optical connector comprises a fiber array unit (FAU), where the FAU has a turn. In an embodiment, the optical connector further comprises a fiber shuffler, where the fiber shuffler comprises a first V-groove with a first depth and a second V-groove with a second depth that is greater than the first depth. In an embodiment, the optical connector further comprises a ferrule.

Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

Abstract: In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between overlapping areas of the bitlines and the wordlines. The bitlines/wordlines include a set of bitlines/wordlines of a first layer that traverse row/column termination tiles and main memory tiles adjacent the row/column termination tiles, with each bitline/wordline of the set of bitlines/wordlines connected to another bitline of a second layer in the termination tile.

Abstract: An apparatus to facilitate combined denoising and upscaling network with importance sampling in a graphics environment is disclosed. The apparatus includes set of processing resources including circuitry configured to: receive, at an input of a density map neural network, a sampled signal of a current frame and a reconstructed sample of the current frame; output, from the density map neural network, a prediction of a density map of samples based on the input of the current frame; provide the density map of samples to a sampler; reproject the density map of samples to a next frame; and apply the reprojected density map of samples to the next frame to generate a next sampled signal.

Abstract: Examples described herein relate to a circuit board that includes a device, firmware memory, and a power controller. In some examples, the firmware memory is to store a firmware update and in response to a software-initiated command, the power controller is to reduce power to the device to cause a firmware update of the device and restore power to the device to cause execution of the firmware update. In some examples, the power controller is to reduce power solely to the device independent from power supply to at least one other device. In some examples, device configuration is saved prior to reduction of power to the device and restored to the device after power is restored to the device.

Abstract: Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.