Abstract: A light emitting device includes a substrate, a light emitting element, a light reflecting resin member, a sealing member, an electrically conductive wiring and a lens member. The light reflecting resin member surrounds the light emitting element. The sealing member is disposed in a region surrounded by the light reflecting resin member. The electrically conductive wiring is arranged on an upper surface of the substrate such that the substrate includes an exposed region exposed from the electrically conductive wiring with at least a part of the exposed region of the substrate being embedded in the light reflecting resin member. The lens member is disposed above the light emitting element to reach an outer edge of the substrate. The lens member is in contact with an upper surface of the sealing member and an upper surface and an outer lateral surface of the light reflecting resin member.

Abstract: When controlling values of a plurality of parameters in a predetermined device according to an operation by a user, values of parameters to be controlled are displayed in an array along an item axis on a parameter editing screen, an operation by the user to the parameter editing screen is detected, and when an operation to trace the screen in a direction of the item axis from a certain position is detected, a sequential control is performed, sequentially according to progress of the operation, to temporarily change to a specific value a value of each parameter corresponding to a position in the item axis direction where the trace operation is being performed.

Abstract: A light emitting diode (LED) is disclosed comprising a plurality of semiconductor layers with a first contact on the bottom surface of the semiconductor layers and a second contact on the top surface of the semiconductor layer. A coating is included that comprises a cured binder and a conversion material that at least partially covers the semiconductor layers, wherein the second contact extends through the coating and is exposed on the same plane as the top surface of the coating. An electrical signal applied to the first and second contacts is conducted through the coating to the semiconductor layers causing the LED to emit light. In other embodiments first and second contacts are accessible from one side of the LED. A coating is included that comprises a cured binder and a conversion material. The coating at least partially covers the semiconductor layers, with the first and second contacts extending through the coating and exposed on the same plane as a surface of the coating.

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Abstract: A display panel includes a substrate having a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer on the substrate; and a transparent conductive layer disposed on the border region and including an opening disposed on the active layer, wherein an opening area of the opening is larger than an area of the active layer.

Abstract: Examples of lighting equipment provide services to and on behalf of a biomechatronically enhanced organism and/or a biomechatronic component of the organism. Such services include charging, communications, location-related services, control, optimization, client-server functions and distributed processing functionality. The biomechatronically enhanced organism and/or biomechatronic component utilize such services provided by and/or via the lighting equipment to enable, enhance or otherwise influence operation of the organism.

Abstract: A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.

Abstract: The present invention is directed to leadless LED packages and LED displays utilizing white ceramic casings and thin/low profile packages with improved color mixing and structural integrity. In some embodiments, the improved color mixing is provided, in part, by the white ceramic package casing, which can help reflect light emitted from each LED in many directions away from the device. The non-linear arrangement of the LEDs can also contribute to improved color-mixing. The improved structural integrity can be provided by various features in the bond pads that cooperate with the casing for a stronger package structure. Moreover, in some embodiments the thinness/low profile of each package is attributed to its leadless structure, with the bond pads and electrodes electrically connected via through-holes.

Abstract: Electrical device comprising a field effect transistor (FET). The FET includes a substrate with a channel region thereon, the channel region including a film of single-walled carbon nanotubes located on the substrate, metallic source and drain electrodes layers on the channel region and gate structure covering a portion of channel region and located between the metallic source and drain electrode layers. The gate structure includes a gate dielectric layer on the portion of the channel region and a gate electrode layer on the gate dielectric layer. Other non-gate-covered portions of the channel region are located between the source electrode layer and the gate structure and between the drain electrode layer and the gate structure. The FET includes a stoichiometrically oxygen-reduced silicon oxide layer contacting the non-gate-covered portions of the channel region, wherein the stoichiometrically oxygen-reduced silicon oxide composition includes SiOx where x has a value of less than 2.

Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.

Abstract: A method for fabricating an optoelectronic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at the adhesion layer by mechanically yielding the adhesion layer. A conductive layer is applied to the material layer on a side opposite the release tape to form a transfer substrate. The transfer substrate is transferred to a target substrate to join the target substrate to the conductive layer of the transfer substrate. The release tape is removed from the material layer to form a top emission optoelectronic device.

Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.