Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes at least one pixel, and each pixel includes N subpixels, wherein each of the subpixels comprises a detection region, two first conductive contacts, wherein the detection region is between the two first conductive contacts, wherein N is a positive integer and is ?2.

Abstract: A semiconductor structure includes a substrate having first and second wells of first and second conductivity types respectively. From a top view, the first and second wells extend lengthwise along a first direction, the first and second wells each includes a protruding section that protrudes along a second direction perpendicular to the first direction and a recessed section that recedes along the second direction. The protruding section of the first well fits into the recessed section of the second well, and vice versa. The semiconductor structure further includes first source/drain features over the protruding section of the first well; second source/drain features over the second well; third source/drain features over the protruding section of the second well; and fourth source/drain features over the first well. The first and second source/drain features are of the first conductivity type. The third and fourth source/drain features are of the second conductivity type.

Abstract: Semiconductor device includes substrate having fins, first S/D feature comprising first epitaxial layer contacting first fin, second epitaxial layer on first epitaxial layer, third epitaxial layer on second epitaxial layer, third epitaxial layer comprising center and edge portion higher than center portion, and fourth epitaxial layer on third epitaxial layer, second S/D feature adjacent first S/D feature and comprising first epitaxial layer contacting second fin, second epitaxial layer on first epitaxial layer of second S/D feature, third epitaxial layer on second epitaxial layer of second S/D feature, third epitaxial layer comprising center and edge portion higher than center portion of third epitaxial layer, center and edge portions of third epitaxial layer of first and second S/D features are merging, and fourth epitaxial layer on third epitaxial layer of second S/D feature, S/D contact covering edge and center portions of third epitaxial layers of first and second S/D features.

Abstract: An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.

Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.

Abstract: A light-emitting device includes a semi-transmissive reflection layer, a first reflection layer that is disposed in a first sub-pixel, a first pixel electrode that is disposed in the first sub-pixel, a first color filer that is disposed in the first sub-pixel, a second reflection layer that is disposed in a second sub-pixel, a second pixel electrode that is disposed in the second sub-pixel, a second color filter that is disposed in the second sub-pixel, the second color filter that is same color as the first color filter, a light-emitting functional layer, and an insulating layer that is disposed between the first reflection layer and the first pixel electrode, the light-emitting functional layer that is disposed between the second reflection layer and the second pixel electrode. A thickness of the insulating layer in the second sub-pixel is thicker than a thickness of the insulating layer in the first sub-pixel.

Abstract: An embodiment device includes: an isolation region on a substrate; a first fin extending above a top surface of the isolation region; a gate structure on the first fin; and an epitaxial source/drain region adjacent the gate structure, the epitaxial source/drain region having a first main portion and a first projecting portion, the first main portion disposed in the first fin, the first projecting portion disposed on a first sidewall of the first fin and beneath the top surface of the isolation region.

Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure includes a base layer, an isolating layer over the base layer, and a stack of channel layers and first sacrificial layers alternately stacked over the isolating layer. The method further includes forming an isolation structure adjacent to sidewalls of the fin structure, wherein a top surface of the isolation structure is above a bottom surface of the isolating layer and below a top surface of the isolating layer. The method further includes depositing a second sacrificial layer over the isolation structure and over the sidewalls of the fin structure; etching the second sacrificial layer and the fin structure to form two source/drain trenches, wherein the source/drain trenches expose the base layer; partially removing the first and the second sacrificial layers through the source/drain trenches to form gaps; and depositing a dielectric spacer in the gaps.

Abstract: A method comprises depositing a barrier layer on a dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to an oxide present in the dielectric layer and depositing a doped liner layer on the barrier layer to bond with the metal layer to be deposited on the liner layer by the electroplating. The dopant forms a protective passivation layer on a surface of the liner layer and dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating bonds with the liner layer. The dopant reacts with the dielectric layer and forms a layer of a compound between the barrier layer and the dielectric layer. The compound layer prevents oxidation of the barrier layer and the liner layer due to the oxide present in the dielectric layer and adheres the barrier layer to the dielectric layer.

Abstract: Aspects of the disclosure provide a method of forming a semiconductor apparatus. A stack of dielectric layers is formed over a semiconductor layer on a substrate of the semiconductor apparatus. Multiple openings are formed in the stack of dielectric layers. Multiple pillars including first sub-pillars and second sub-pillars are formed in the multiple openings. A cantilever structure that includes a first cantilever beam and a second cantilever beam is formed. A cantilever supporting structure that includes a portion of a first subset of the multiple pillars is formed. The first cantilever beam connects the second cantilever beam and the cantilever supporting structure. One of the stack of dielectric layers is removed to expose first portions of the first sub-pillars and second portions of the second sub-pillars. Isolation structures are formed between the first sub-pillars and the respective second sub-pillars.

Abstract: An integrated circuit includes a standard cell continuously arranged on a first row and on a second row, the first row and second row extending parallel with each other in a first direction, the first row and the second row adjacent to each other in a second direction crossing the first direction, a first cell separator contacting a first row boundary of the standard cell on the first row and extending in the second direction, and a second cell separator contacting a second row boundary of the standard cell on the second row and extending in the second direction. The first cell separator and the second cell separator are discontinuous on a first row to second row boundary of the first row and the second row.

Abstract: An operation method and an electronic device are provided. A phone call is established while a display of the electronic device is activated. A proximity sensor of the electronic device is turned on. A supply of power to the proximity sensor is controlled to emit light through a plurality of pixels in a portion of the display corresponding to a position of the proximity sensor and the light emitted by the proximity sensor and reflected by an object is received to identify a distance between the electronic device and the object, if the plurality of the pixels in the position corresponding to the proximity sensor are deactivated during the phone call. The supply of power to the proximity sensor is blocked if the plurality of pixels in the portion of the display corresponding to the proximity sensor are activated during the phone call.

Abstract: Embodiments of the present disclosure provide an OLED device, a method of manufacturing the OLED device, and a display panel. The OLED device comprises: a substrate, a first electrode layer, a color filter layer, a light emitting layer and a second electrode layer. The first electrode layer is one of an anode layer and a cathode layer and comprises: a first sub-electrode layer disposed on the substrate; and a second sub-electrode layer electrically connected with the first sub-electrode layer. The color filter layer is disposed on the first sub-electrode layer and the second sub-electrode layer is disposed on the color filter layer. The second electrode layer is the other of the anode layer and the cathode layer and the light emitting layer is disposed between the second electrode layer and the second sub-electrode layer of the first electrode layer.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region, and an isolation region positioned between the first active region and the second active region; and a gate layer crossing over the first active region, the second active region, and the isolation region, wherein the gate layer includes a first impurity doped portion overlapping with the first active region, a second impurity doped portion overlapping with the second active region, and a diffusion barrier portion positioned between the first impurity doped portion and the second impurity doped portion.

Abstract: A stress isolating interposer includes: an outer pad; an inner pad configured to accommodate a positional sensor is mounted; and a stress isolating structure coupling the outer pad and the inner pad to each other. The outer pad, the stress isolating structure, and the inner pad are a monolithic structure.

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.