Abstract: To prevent short defects between source/drains of transistors of a complementary cell circuit, isolation walls are formed in an isolation region between the source/drains of the transistors prior to growing a P-type epitaxial layer and an N-type epitaxial layer on respective sides of the isolation region. The isolation walls provide a physical barrier to prevent formation of short defects that can otherwise form between the P-type and N-type epitaxial layers. Thus, the isolation walls prevent circuit failures resulting from electrical shorts between source/drain regions of transistors in complementary cell circuits. A width of the isolation region between a P-type transistor and an N-type transistor in a circuit cell layout can be reduced so that a total layout area of the complementary cell circuit can be reduced without reducing product yield. A gate cut may be formed in the dummy gate with a process of forming the isolation walls.

Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

Abstract: A semiconductor device includes a silicon carbide layer, a metal carbide layer arranged over the silicon carbide layer, and a solder layer arranged over and in contact with the metal carbide layer.

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

Abstract: A display panel, a display device, and a manufacturing method of the display panel are disclosed. The display panel includes: a light emitting element including a microcavity structure and a light emitting layer disposed in the microcavity structure; and an external microcavity structure disposed on a light emitting side of the light emitting element and including a first transflective layer, a second transflective layer and a dielectric layer disposed between the first transflective layer and the second transflective layer. The microcavity structure can modulate a spectrum of light emitted by the light emitting layer in the first viewing angle range; the external microcavity structure can modulate a spectrum of light emitted by the light emitting element in the second viewing angle range; and the second viewing angle range is greater than the first viewing angle range.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region, a second region and a third region; forming a dielectric layer on the base substrate; forming a first mask layer on the dielectric layer in the second region; forming a second mask layer on sidewall surfaces of the first mask layer and on the dielectric layer in the second region; etching the dielectric layer in the first region and the third region using the first mask layer and the second mask layer as an etching mask to form a first trench in the first region and a first trench in the third region; removing the first mask; and etching the dielectric layer in the second region using the second mask layer as an etching mask to form a second trench in the dielectric layer in the second region.

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material, where the SOT material includes iridium and manganese and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, a fixed layer and a tunnel barrier between the free layer and the fixed layer and a SAF structure above the fixed layer. The Ir—Mn SOT material and the free magnet have an in-plane magnetic exchange bias.

Abstract: A semiconductor device includes a plurality of first memory cells in a memory region and a first cut-off transistor in a dummy region, the dummy region being adjacent to the memory region. Each of the plurality of the first memory cells includes a static random access memory (SRAM) cell. The static random access memory cell includes a first pull-down transistor and a second pull-down transistor. The plurality of the first memory cells includes a first memory cell. A first source/drain region of the first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first cut-off transistor and a second source/drain region of the first cut-off transistor is electrically coupled to a power supply voltage.

Abstract: A semiconductor structure and forming method are provided. The method includes providing a substrate, forming a gate structure over the substrate, forming a first spacer on a sidewall of the gate structure; forming an epitaxial layer on both sides of the gate structure and the first spacer, a surface of the epitaxial layer is higher than a surface of the substrate; forming a dielectric layer on the epitaxial layer and on surface of the first spacer, the dielectric layer is formed on both sides of the gate structure; after forming the dielectric layer, removing the first spacer to form a first opening between the epitaxial layer and the gate structure and between the dielectric layer and the gate structure, and in the first opening forming a second spacer that has a gap between the epitaxial layer and the gate structure.

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization; an interconnect adjacent to the magnetic junction, wherein the interconnect comprises an antiferromagnetic (AFM) material which is doped with a doping material (Pt, Ni, Co, or Cr) and a structure adjacent to the interconnect such that the magnetic junction and the structure are on opposite surfaces of the interconnect, wherein the structure comprises a magnet with a second magnetization substantially different from the first magnetization.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

Abstract: A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated.

Abstract: A semiconductor device that includes a fin structure, and a channel epitaxial wrap around layer at each end of a channel portion of the fin structure. The semiconductor device also includes a gate structure including a gate dielectric having gate edge portions in direct contact with the channel epitaxial wrap around layer. A middle portion of the gate dielectric is in direct contact with a central channel portion of the fin structure between the two ends of the channel portion of the fin structure. Source and drain regions are present on opposing sides of the channel portion of the fin structure.

Abstract: A method for calibration including determining a temperature induced offset in a pedestal of a process module under a temperature condition for a process. The method includes delivering a wafer to the pedestal of the process module by a robot, and detecting an entry offset. The method includes rotating the wafer over the pedestal by an angle. The method includes removing the wafer from the pedestal by the robot and measuring an exit offset. The method includes determining a magnitude and direction of the temperature induced offset using the entry offset and exit offset.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, which includes a first region, a second region, and a third region. The semiconductor structure also includes a first fin, a second fin, and a third fin formed on the first, second, and third regions, respectively. Moreover, the semiconductor structure includes an isolation layer formed on the substrate, and a portion of sidewall surface of each of the first, second, and third fins. In addition, the semiconductor structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer formed on the first, second, and third fins, respectively. Two sides of the third epitaxial layer are in contact with the first epitaxial layer and the second epitaxial layer, respectively. Further, the semiconductor structure includes a conductive structure formed on the first, second, and third epitaxial layers.

Abstract: Wrap-around contact structures for semiconductor fins, and methods of fabricating wrap-around contact structures for semiconductor fins, are described. In an example, an integrated circuit structure includes a semiconductor fin having a first portion protruding through a trench isolation region. A gate structure is over a top and along sidewalls of the first portion of the semiconductor fin. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor fin. The epitaxial structure has substantially vertical sidewalls in alignment with the second portion of the semiconductor fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: A spin orbit torque (SOT) memory device includes a MTJ device on a SOT electrode, where a first portion of the SOT electrode extends beyond a sidewall of the MTJ by a first length that is no greater than a height of the MTJ, and where a second portion of the first electrode extends from the sidewall and under the MTJ by a second length that is no greater than a width of the MTJ. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet.

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.