Abstract: An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.

Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.

Abstract: A semiconductor device having a semiconductor substrate that includes first to third epitaxial layers provided sequentially on a starting substrate, the third epitaxial layer forming a pn junction with the second epitaxial layer, and including a plurality of first semiconductor regions formed on a second semiconductor region. The semiconductor device further includes a plurality of trenches penetrating the first and second semiconductor regions to reach the second epitaxial layer, a plurality of gate electrodes provided in the trenches respectively via a gate insulating film, a metal film in ohmic contact with the first semiconductor regions, a first electrode electrically connected to the first semiconductor regions via the metal film, and a second electrode provided at a back surface of the starting substrate. Each of the starting substrate and the first to third epitaxial layers contains silicon carbide.

Abstract: An imaging device includes: a semiconductor layer including a first region of a first conductivity, a second region of a second conductivity opposite to the first conductivity, and a third region of the second conductivity; a photoelectric converter electrically connected to the first region and converting light into charge; a first transistor including a first source, a first drain, and a first gate above the second region, the first region corresponding to the first source or drain; and a second transistor including a second source, a second drain, and a second gate of the second conductivity above the third region, the first region corresponding to the second source or drain, and the second gate being electrically connected to the first region. The concentration of an impurity of the second conductivity in the third region is higher than that of an impurity of the second conductivity in the second region.

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects provided in I/O cell rows are connected to a power supply interconnect provided between the I/O cell rows via power supply interconnects. The power supply interconnect is thicker than the in-row power supply interconnects.

Abstract: A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.

Abstract: A method of transferring a thin film from a substrate to a flexible support that includes transfer of the flexible support by a layer of polymer, crosslinkable under ultraviolet light, directly on the thin film, the adhesion energy of the polymer evolving according to its degree of crosslinking, decreasing to an energy point d minimum adhesion achieved for a nominal crosslinking rate, then increasing for a crosslinking rate greater than the nominal crosslinking rate, then apply, on the polymer layer, an ultraviolet exposure parameterized so as to stiffen the polymer layer and have an adhesion energy between the thin film and the flexible support greater than an adhesion energy between the thin film and the substrate, then remove the substrate.

Abstract: The present application provides an array substrate. The array substrate includes a base substrate; a light shielding layer on the base substrate; a metal oxide layer on a side of the light shielding layer distal to the base substrate; and an active layer on a side of the metal oxide layer distal to the base substrate. The metal oxide layer includes a metal oxide material. The light shielding layer includes amorphous silicon. An orthographic projection of the light shielding layer on the base substrate substantially overlaps with an orthographic projection of the active layer on the base substrate, and substantially overlaps with an orthographic projection of the metal oxide layer on the base substrate.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first isolation feature in a peripheral region of a substrate; recessing the cell region of the substrate after forming the first isolation feature; forming a second isolation feature in a cell region of the substrate after recessing the cell region of the substrate; forming a plurality of control gates over the cell region of the substrate; and forming a gate stack over the peripheral region of the substrate.

Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.

Abstract: A carrier structure includes: a plurality of substrates; a separation portion provided between the substrates; and a periphery portion provided at the periphery of the substrates and formed with at least one opening. With the configuration of the opening, the area of an insulating layer of the carrier structure can be reduced. Therefore, the overall space of electrostatic buildup in the carrier structure can also be reduced.

Abstract: A method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature. The method further includes forming a hole in the dielectric layer to expose the conductive feature; forming a first metal-containing layer on sidewalls of the hole; and forming a second metal-containing layer in the hole and surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. The method further includes applying a first chemical to recess the dielectric layer, resulting in a top portion of the first and the second metal-containing layers protruding above the dielectric layer; and applying a second chemical having fluorine or chlorine to the top portion of the first metal-containing layer to convert the top portion of the first metal-containing layer into a metal fluoride or a metal chloride.

Abstract: The present disclosure provides systems and methods for a layered substrate. A layered substrate may include a core comprising graphite. The layered substrate may also include a coating layer comprising a coating material that surrounds the core, wherein the coating material has a melting point that is greater than a melting point of silicon.

Abstract: The invention provides a quantum dot manufacturing method and related quantum dot semiconductor structure. The quantum dot semiconductor structure includes: a conductive ridge on a substrate; an insulative layer covering the substrate and the conductive ridge, wherein the insulative layer includes a top portion and two sidewalls over the conductive ridge; a plurality of quantum dots respectively embedded within a plurality of silicon dioxide spacer islands, which are adhered to the sidewalls of the insulative layer; and a plurality of conductive ledges adhered to the silicon dioxide spacer islands, wherein each of the conductive ledges is a portion of an electrode with alignment to the corresponding quantum dot.

Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

Abstract: A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.

Abstract: The first gate insulating film is an insulating film made of silicon oxide, and to which hafnium (Hf) is added without addition of aluminum (Al). Also, the second gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added without addition of hafnium. The third gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added. Further, the fourth gate insulating film is an insulating film made of silicon oxide, and to which hafnium is added. Accordingly, it is possible to reduce the power consumption of the semiconductor device.

Abstract: A method of transferring semiconductor devices from a first substrate to a second substrate, including providing the semiconductor devices which are between the first substrate and the second substrate. The semiconductor devices include a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof. The first semiconductor device and the second semiconductor device are moved from the first substrate by a picking unit. The picking unit, the first semiconductor device, and the second semiconductor device are moved close to the second substrate. The picking unit has a space apart from the second substrate. The first semiconductor device and the second semiconductor device are transferred from the picking unit to the second substrate. The he first semiconductor device and the second semiconductor device on the second substrate have a second gap between thereof. The first gap and the second gap are different.

Abstract: A method for selectively modifying a base material surface, includes applying a composition on a surface of a base material to form a coating film. The coating film is heated. The base material includes a surface layer which includes a first region including silicon. The composition includes a first polymer and a solvent. The first polymer includes at an end of a main chain or a side chain thereof, a group including a first functional group capable of forming a bond with the silicon. The first region preferably contains a silicon oxide, a silicon nitride, or a silicon oxynitride. The base material preferably further includes a second region that is other than the first region and that contains a metal; and the method preferably further includes, after the heating, removing with a rinse agent a portion formed on the second region, of the coating film.