Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

Abstract: A wafer composite includes a handle substrate, an auxiliary layer formed on a first main surface of the handle substrate, and a silicon carbide structure formed over the auxiliary layer. The handle substrate is subjected to laser radiation that modifies crystalline material along a focal plane in the handle substrate. The focal plane is parallel to the first main surface. The auxiliary layer is configured to stop propagation of microcracks that the laser radiation may generate in the handle substrate.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

Abstract: A fin height monitoring structure including a substrate, isolation structures, a first word line, and a second word line is provided. The substrate includes a first region and a second region. The isolation structures are located in the substrate of the first region to define at least one active area. The substrate in the active area has a fin that is higher than the isolation structures. The first word line is located on the isolation structures of the first region and on the fin of the first region. The second word line is located on the substrate of the second region.

Abstract: Disclosed herein is an apparatus for adjusting the installation location of a temperature sensor configured to measure the surface temperature of a wafer in a semiconductor wafer cleaning apparatus. The apparatus includes: a bracket which is disposed in the upper end of the side wall of each of multi-station processing chambers (MPCs); a first fastening member which fastens a cable; a second fastening member which fastens a temperature sensor; a location adjustment member which fastens and supports the temperature sensor; the temperature sensor which is fixedly coupled to an end of the location adjustment member; a jig which includes a location adjustment plate and a control substrate, and which adjusts the detection location of the temperature sensor; and a controller which is provided with a wafer surface monitoring system configured to separate the surface temperature into a plurality of channels and to display the surface temperature.

Abstract: Embodiments of this disclosure include apparatus, systems, and methods for fabricating monolayers. In one example, a method includes forming a multilayer film having a plurality of monolayers of a two-dimensional (2D) material on a growth substrate. The multilayer film has a first side proximate the growth substrate and a second side opposite the first side.

Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) having a nanosheet stack formed over a substrate. The nanosheet stack includes a plurality of channel nanosheets, wherein the plurality of channel nanosheets includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region and the second end region include a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region includes a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.

Abstract: An electrical isolation process, includes receiving a substrate including a layer of carbon-rich material on silicon, and selectively removing regions of the substrate to form mutually spaced islands of the carbon-rich material on the silicon. The layer of carbon-rich material on silicon includes the layer of carbon-rich material on an electrically conductive layer of silicon on an electrically insulating material. Selectively removing regions of the substrate includes removing the carbon-rich material and at least a portion of the electrically conductive layer of silicon from those regions to provide electrical isolation between the islands of carbon-rich material on silicon.

Abstract: A formulation comprising an n-type organic semiconductor, a p-type organic semiconductor and a solvent mixture comprising a first solvent and a second solvent wherein the first solvent is an alkylated aromatic hydrocarbon, for example trimethylbenzene, and the second solvent is a benzene substituted with two or more substituents including at least two C1-6 alkoxy groups, for example dimethoxybenzene. The formulation may be used to form the photoactive layer (3) of a photosensitive organic electronic device, for example an organic photo detector, comprising an anode (2) a cathode (4) and the photoactive layer between the anode and the cathode.

Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.

Abstract: Provided is a method of manufacturing a nanowire semiconductor device, the method including: forming a seed layer on a substrate; forming, on the seed layer, a multilayer in which a first conductive layer, a semiconductor layer, a second conductive layer are sequentially stacked; forming a vertical nanowire above the substrate by patterning the multilayer; crystallizing the vertical nanowire by heat treatment; forming an insulating layer covering the vertical nanowire; forming a gate surrounding a channel area by the semiconductor silicon layer of the vertical nanowire; and forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer.

Abstract: A monitoring device for monitoring a fabrication process in a fabrication system. The monitored fabrication system includes a process chamber and a plurality of flow components. A quartz crystal microbalance (QCM) sensor monitors one flow component of the plurality of flow components of the fabrication system and is configured for exposure to a process chemistry in the one flow component during the fabrication process. A controller measures resonance frequency shifts of the QCM sensor due to interactions between the QCM sensor and the process chemistry in the one flow component during the fabrication process. The controller determines a parameter of the fabrication process in the process chamber as a function of the measured resonance frequency shifts of the QCM sensor within the one flow component.

Abstract: A security region is provided. The security region includes a plurality of parallel conductive lines on a substrate, wherein each of the parallel conductive lines has a width and includes a bend, and wherein at least a portion of the plurality of parallel conductive lines is discontinuous, and an electrically insulating material between each adjacent pair of parallel conductive lines.