Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face opposite to the first face, and including a p-type silicon carbide region in contact with the first face, a percentage of a first silicon atom among a plurality of silicon atoms present in a first layer as an uppermost layer being equal to or more than 90% and a site position of the first silicon atom being different from a site position of a silicon atom in a third layer from the first face and the same as a site position of a silicon atom in a fifth layer from the first face; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer including nitrogen.

Abstract: Systems and methods are provided for monitoring wafer bonding and for detecting or determining defects in a wafer bond formed between two semiconductor wafers. A wafer bonding system includes a camera configured to monitor bonding between two semiconductor wafers. Wafer bonding defect detection circuitry receives video data from the camera, and detects a bonding defect based on the received video data.

Abstract: Redeposition of substrate material on a fiducial resulting from charged particle beam (CPB) or laser beam milling of a substrate can be reduced with a shield formed on the substrate surface. The shield typically has a suitable height that can be selected based on proximity of an area to be milled to the fiducial. The shield can be formed with the milling beam using beam-assisted chemical vapor deposition (CVD). The same or different beams can be used for milling and beam-assisted CVD.

Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.

Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10?2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

Abstract: A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.

Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).

Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

Abstract: A depth sensor includes a first pixel including a plurality of first photo transistors each receiving a first photo gate signal, a second pixel including a plurality of second photo transistors each receiving a second photo gate signal, a third pixel including a plurality of third photo transistors each receiving a third photo gate signal, a fourth pixel including a plurality of fourth photo transistors each receiving a fourth photo gate signal, and a photoelectric conversion element shared by first to fourth photo transistors of the plurality of first to fourth photo transistors.

Abstract: The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.

Abstract: A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.

Abstract: The invention provides a method 100 of manufacturing a precursor 105a for use in manufacturing a semiconductor-on-diamond substrate 110, the method comprising: a) starting with a base substrate 112; b) forming a sacrificial carrier layer 114 on the base substrate, the sacrificial carrier layer comprising a single-crystal semiconductor; c) forming a single-crystal nucleation layer 116 on the sacrificial carrier layer, the single-crystal nucleation layer arranged to nucleate diamond growth; and d) forming a device layer 118 on the single-crystal nucleation layer, the device layer comprising a single-crystal semiconductor layer or multiple single-crystal semiconductor layers.

Abstract: A method for manufacturing a semiconductor device, includes: forming an alignment mark in a non-element region of a gallium-based compound semiconductor layer; and, after the forming of the alignment mark, forming an element structure in an element region of the gallium-based compound semiconductor layer. The forming of the alignment mark further includes: ion-implanting a metal into a part of a surface layer portion of the non-element region of the gallium-based compound semiconductor layer; and annealing the gallium-based compound semiconductor layer.

Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.

Abstract: A process apparatus includes a heating module and a supporter disposed below the heating module. A process space is provided between the heating module and the supporter. The heating module includes a housing, at least one heating lamp disposed in the housing, at least one temperature sensor disposed in the housing, and a blocking plate disposed under the housing. The blocking plate spatially separates the at least one heating lamp from the process space, and the blocking plate includes at least one window spatially connecting the at least one temperature sensor to the process space.

Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.