Patents Examined by Alexander G. Ghyka
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Patent number: 11776838Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.Type: GrantFiled: November 15, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
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Patent number: 11764087Abstract: A process apparatus includes a heating module and a supporter disposed below the heating module. A process space is provided between the heating module and the supporter. The heating module includes a housing, at least one heating lamp disposed in the housing, at least one temperature sensor disposed in the housing, and a blocking plate disposed under the housing. The blocking plate spatially separates the at least one heating lamp from the process space, and the blocking plate includes at least one window spatially connecting the at least one temperature sensor to the process space.Type: GrantFiled: June 11, 2020Date of Patent: September 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chaemook Lim, Yeongrack Son, Ohhyuk Kwon, Dongouk Kim, Youngbum Kim, Woohee Kim, Dongjoon Lee, Kwanghyeon Jeong
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Patent number: 11756827Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.Type: GrantFiled: April 20, 2022Date of Patent: September 12, 2023Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Fumimasa Horikiri, Noboru Fukuhara
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Patent number: 11745415Abstract: An optoelectronic semiconductor component and a 3D printer are disclosed. In an embodiment the component includes a carrier and a plurality of individually controllable pixels, wherein the pixels are mounted on the carrier and are formed from at least one semiconductor material, and wherein the pixels are configured to emit radiation having a wavelength of maximum intensity of 470 nm or less.Type: GrantFiled: February 1, 2021Date of Patent: September 5, 2023Assignee: OSRAM OLED GmbHInventors: Nikolaus Gmeinwieser, Norwin von Malm
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Patent number: 11728247Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first tier includes forming a conductive via extending from a lower portion of a first interconnect structure into a first semiconductor substrate underlying the lower portion; forming an upper portion of the first interconnect structure on the conductive via and the lower portion; forming a first surface dielectric layer on the upper portion; and forming a first and a second bonding connectors in the first surface dielectric layer. The first bonding connector extends to be in contact with an upper-level interconnecting layer of the first interconnect structure, the second bonding connector is narrower than the first bonding connector and extends to be in contact with a lower-level interconnecting layer of the first interconnect structure, and a top surface of the conductive via is between the upper-level interconnecting layer and the first semiconductor substrate.Type: GrantFiled: July 2, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan
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Patent number: 11730039Abstract: A method for fabricating a touch display substrate and a touch display substrate are provided to solve the problem that existing touch electrodes of the micron-scale line width cannot meet the high PPI requirement. The fabrication method includes forming functional layers of an organic light-emitting diode (OLED) device on a base substrate sequentially to obtain an OLED substrate; and forming a linear touch electrode with a nano-scale line width on the OLED substrate by electronic sputtering and transferring.Type: GrantFiled: May 6, 2020Date of Patent: August 15, 2023Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yingming Liu, Xue Dong, Haisheng Wang, Chunwei Wu, Xiaoliang Ding, Rui Xu, Lijun Zhao, Changfeng Li, Yanan Jia, Yuzhen Guo, Yunke Qin, Pinchao Gu
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Patent number: 11710636Abstract: Metal spacer-based approaches for fabricating conductive lines/interconnects are described. In an example, an integrated circuit structure includes a substrate. A first spacer pattern is on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W1). A second spacer pattern is on the substrate, where the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W2) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers.Type: GrantFiled: June 20, 2018Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Kevin Lin, Charles Wallace
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Patent number: 11705368Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: GrantFiled: July 13, 2021Date of Patent: July 18, 2023Assignee: XINTEC INC.Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
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Patent number: 11699586Abstract: A method of manufacturing nitride semiconductor substrate, comprising: providing silicon-on-insulator substrate which comprises an underlying silicon layer, a buried silicon dioxide layer and a top silicon layer; forming a first nitride semiconductor layer on the top silicon layer; forming, in the first nitride semiconductor layer, a plurality of notches which expose the top silicon layer; removing the top silicon layer and forming a plurality of protrusions and a plurality of recesses on an upper surface of the buried silicon dioxide layer, wherein each of the plurality of protrusions is in contact with the first nitride semiconductor layer, and there is a gap between each of the plurality of recesses and the first nitride semiconductor layer; and epitaxially growing a second nitride semiconductor layer on the first nitride semiconductor layer, such that the first nitride semiconductor layer and the second nitride semiconductor layer form a nitride semiconductor substrate.Type: GrantFiled: August 13, 2019Date of Patent: July 11, 2023Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 11699672Abstract: A semiconductor device includes a pad formed on a surface of a substrate, a bonding wire for connecting the pad to an external circuit, and a resin layer covering at least a connection portion between the pad and the bonding wire and exposing at least a part of the substrate outside the pad.Type: GrantFiled: July 9, 2021Date of Patent: July 11, 2023Assignee: DENSO CORPORATIONInventors: Mariko Fujieda, Kazuaki Mawatari, Shinji Kawano
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Patent number: 11699588Abstract: A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.Type: GrantFiled: March 15, 2022Date of Patent: July 11, 2023Inventor: Ying Hong
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Patent number: 11694891Abstract: A film forming apparatus comprises: a processing chamber in which a substrate is accommodated; a gas supply configured to supply a gas containing a first monomer and a gas containing a second monomer into the processing chamber; a concentration distribution controller configured to control a gas flow within the processing chamber such that a concentration of a mixed gas including the gas containing the first monomer and the gas containing the second monomer on the substrate has a predetermined distribution; and a temperature distribution controller configured to control a temperature distribution of the substrate such that a temperature of a first region of the substrate is higher than a temperature of a second region of the substrate, the concentration of the mixed gas in a region corresponding to the first region being higher than the concentration of the mixed gas in a region corresponding to the second region.Type: GrantFiled: July 28, 2020Date of Patent: July 4, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Syuji Nozawa, Tatsuya Yamaguchi
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Patent number: 11688651Abstract: Provided is a semiconductor structure including a substrate, at least two tested structures, an isolation structure, and a short-circuit detection structure. At least two tested structures are disposed on the substrate. The at least two tested structures include a conductive material. The isolation structure is sandwiched between at least two tested structures. The detection structure includes a detecting layer, and the detecting layer is disposed on one of the at least two tested structures, so that a short circuit defect between the at least two tested structures may be identified in an electron beam detecting process, and the detecting layer includes a conductive material. A manufacturing method of the semiconductor structure and a method for detecting a short circuit of the semiconductor structure are also provided.Type: GrantFiled: March 4, 2020Date of Patent: June 27, 2023Assignee: Winbond Electronics Corp.Inventors: Hung-Ming Su, Kazuaki Takesako, Chun-Chiao Tseng
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Patent number: 11682555Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.Type: GrantFiled: April 7, 2021Date of Patent: June 20, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-woon Park, Jin-su Lee, Hyung-suk Jung
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Patent number: 11682584Abstract: There may be provided a method for inspecting a top redistribution layer conductors of an object. The top redistribution layer (RDL) is positioned above at least one lower RDL and above at least one other dielectric layer. The method may include (i) illuminating the object with radiation, the at least one lower dielectric layer significantly absorbs the radiation; (ii) generating, by a detector, detection signals that represent radiation reflected from the object, and (iii) processing, by a processor, the detection signal to provide information about the top RDL. The processing may include distinguishing detection signals related to the top RDL from detection signals related to the at least one lower RDL.Type: GrantFiled: December 24, 2019Date of Patent: June 20, 2023Assignee: CAMTEK LTD.Inventor: Zehava Ben Ezer
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Patent number: 11682595Abstract: A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.Type: GrantFiled: February 22, 2021Date of Patent: June 20, 2023Assignee: Western Digital Technologies, Inc.Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
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Patent number: 11676860Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.Type: GrantFiled: October 19, 2018Date of Patent: June 13, 2023Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.Inventors: Allen W. Hanson, Rajesh Baskaran, Timothy E. Boles
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Patent number: 11670543Abstract: Embodiments of methods for forming a hybrid-bonded semiconductor structure are disclosed. The method include disposing first second, third, and fourth dielectric layers, forming first and second openings by etching the fourth dielectric layer using a first etching selectivity, etching the third and fourth dielectric layers in the first and second openings respectively using a second etching selectivity, etching the second and third dielectric layers in the first and second openings using the first etching selectivity, etching the first dielectric layer in the first opening and the second dielectric layer in the second opening using the second etching selectivity, etching the first dielectric layer in the first and second openings using the first etching selectivity, and forming conductive material in the first and second openings.Type: GrantFiled: March 24, 2022Date of Patent: June 6, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Meng Yan, Jifeng Zhu, Si Ping Hu
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Patent number: 11670514Abstract: A method for manufacturing a semiconductor device includes the steps of forming a fixing layer, coupling a third substrate different from the first substrate and the second substrate to the fixing layer, separating the semiconductor thin film layer from the first substrate by moving the third substrate away from the base material substrate with the third substrate coupled to the coupling region, and bonding the semiconductor thin film layer to the second substrate after separation from the base material substrate, wherein the forming the fixing layer forms the fixing layer having a thickness such lhat a crack is generated between the fixing layer formed on the first substrate and the fixing layer formed on a side surface of the semiconductor thin film layer by a force for moving the third substrate.Type: GrantFiled: September 17, 2021Date of Patent: June 6, 2023Assignee: FILNEX INC.Inventor: Mitsuhiko Ogihara
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Patent number: 11664246Abstract: A method for thermally processing a substrate having a surface region and a buried region with a pulsed light beam, the substrate presenting an initial temperature-depth profile and the surface region presenting an initial surface temperature, including steps of: illuminating the surface region with a preliminary pulse so that it generates an amount of heat and reaches a predetermined preliminary surface temperature; and illuminating the surface region with a subsequent pulse after a time interval so that it reaches a predetermined subsequent surface temperature. The time interval is determined such that the surface region reaches a predetermined intermediate surface temperature greater than the initial surface temperature, such that during the time interval, the amount of heat is diffused within the substrate down to a predetermined depth so that the substrate presents a predetermined intermediate temperature-depth profile.Type: GrantFiled: December 3, 2019Date of Patent: May 30, 2023Assignee: LASER SYSTEMS & SOLUTIONS OF EUROPEInventor: Fulvio Mazzamuto