Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Abstract: A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.

Abstract: A mirror device has a plurality of organic EL elements and a plurality of metal mirror surface portions that are divided by banks made of a light-transmissive dielectric material and aligned on a substrate. Each of the organic EL elements has an organic layer that is formed between a light-transmissive electrode and a reflection electrode and contains a light-emitting layer. Each of the metal mirror surface portions and each of the organic EL elements or each group of the metal mirror surface portions and each group of the organic EL elements are alternately disposed.

Abstract: The invention provides a semiconductor cooling method that comprises: providing two wafers which require to be treated by a mixed bonding process, wherein each of the wafers being provided with several metallic device structure layers therein. A heat dissipation layer is set in at least one of the wafers and arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer and the invention provides a method of heat dissipation that comprises providing at least two wafers to be bonded; and arranging some conducting wires on a surface of wafers. In addition, the method includes the steps of performing a bonding process to form a device with bonded wafers, wherein one end of the conducting wires locates in the region where the wafers generate heat, and another end extends to an external of wafers.

Abstract: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

Abstract: A semiconductor structure may be formed by forming a first semiconductor fin and a second inactive semiconductor fin above a substrate; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the masking layer; removing the second semiconductor fin to form a fin recess beneath the trench; filling the fin recess with an insulating material to form an insulating fence fin; and removing the masking layer to expose the first semiconductor fin and the insulating fence fin. A third semiconductor fin separating the first semiconductor fin from the second semiconductor fin may also be formed prior to depositing the masking layer and covered by the masking layer. The first semiconductor fin may be a pFET fin and the third semiconductor fin may be an nFET fin.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract: A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and interconnection region, and a decoupling unit. The integrated circuit die includes a plurality of circuits, which each include multiple devices interconnected using wires fabricated on a first plurality of conductive layers. The interconnection region includes multiple solder balls, and multiple conductive paths, each of which includes wires fabricated on a second plurality conductive layers. At least one solder ball is connected to an Input/Output terminal of a first circuit of the plurality of circuits via one of the conductive paths. The decoupling unit may include a plurality of capacitors and a plurality of terminals. Each terminal of the decoupling unit may be coupled to a respective power terminal of a second circuit of the plurality of circuits via the conductive paths.

Abstract: A semiconductor package structure includes a lead frame, a chip and a molding compound. The lead frame includes a tray pad and a plurality of leads. Two of the leads are different in height positions. The chip is disposed on the tray. The molding compound encapsulates the chip and a portion of each lead.

Abstract: A semiconductor package includes a substrate; a first semiconductor chip arranged on the substrate; a second semiconductor chip arranged on the first semiconductor chip; a lead attached to the second semiconductor chip on a side of the second semiconductor chip opposite a side of the second semiconductor chip facing the first semiconductor chip; and a molding member covering an upper surface of the substrate and side surfaces of the lead and sealing the first semiconductor chip and the second semiconductor chip.

Abstract: A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. Interconnection members are disposed to electrically connect the elastic buffer layer to the substrate. Each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.

Abstract: A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.

Abstract: A memory module is provided. In one example, the memory module includes a printed circuit board with one or more connectors, and a plurality of multi-chip packaged integrated circuit parts mounted to the printed circuit board. Each of the plurality of multi-chip packaged integrated circuit parts includes an integrated circuit package including a slave memory controller (SMC) die and one or more pairs of (1) a spacer under the slave memory controller die and (2) a flash memory die under the spacer. Each flash memory die is larger than each spacer to provide an opening into a perimeter of the flash memory die to which electrical connections may be made.

Abstract: A switching device having a substrate, a power semiconductor component, a connecting device, load connection devices and a pressure device. Substrate has electrically insulated conductor tracks. A power semiconductor component is arranged on a conductor track. Connecting device is formed as a film composite having an electrically conductive film and an electrically insulating film, and has first and second main surfaces. Switching device is connected in an internally circuit-conforming manner by connecting device. The pressure device has a pressure body with a first recess, a pressure element being arranged so that it projects out of the recess, wherein the pressure element presses onto a section of the second main surface of film composite and, in this case, the section is arranged within the surface of the power semiconductor component in projection along the normal direction of the power semiconductor component.

Abstract: A semiconductor assembly includes a frame having at least one opening, an identical number of electrically conductive first contact plates, and an identical number of chip arrays. Each chip array has a number of semiconductor chips that are cohesively connected to one another by an embedding compound. In addition, each of the semiconductor chips has a first load terminal and a second load terminal arranged at mutually opposite sides of the relevant semiconductor chip. One of the chip arrays is inserted into each of the openings. Each of the first contact plates is arranged above one of the chip arrays in such a way that, for each of the semiconductor chips, the first load terminal is situated at a side of said semiconductor chip facing the first contact plate and the second load terminal is situated a of said semiconductor chip facing away from the first contact plate.

Abstract: A semiconductor device that includes a semiconductor chip having a first silicon substrate with opposing first and second surfaces, a semiconductor device formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the semiconductor device, a layer of thermal conductive material on the second surface, and a plurality of first vias formed partially through the layer of thermal conductive material.

Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.

Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.