Abstract: Provided is an organic light emitting diode display device, including a pixel substrate including a pixel unit displaying an image and a peripheral unit surrounding the pixel unit; a first insulating layer covering the pixel substrate; a fanout line on the first insulating layer of the peripheral unit; a second insulating layer covering the first insulating layer and the fanout line; an etching prevention member on the second insulating layer of the peripheral unit and preventing overetching of the second insulating layer; a third insulating layer covering the second insulating layer; a peripheral potential voltage line on the third insulating layer of the peripheral unit and transferring a potential voltage; a passivation layer covering the third insulating layer; and an organic light emitting diode on the passivation layer of the pixel unit, in which the etching prevention member overlaps with the fanout line and the peripheral potential voltage line.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.

Abstract: A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.

Abstract: A semiconductor device includes a semiconductor substrate, and a redistribution layer (RDL) over the semiconductor substrate and configured to receive a bump. The semiconductor device further includes a polymeric material over the RDL, and the polymeric material includes an opening to expose a portion of the RDL. In the semiconductor device, a barrier is covering a joint between the polymeric material and the RDL.

Abstract: A method is disclosed for selecting a semiconductor chip in a stack of semiconductor chips interconnected by through-lines by receiving selection signals at the first terminals located on a first surface of the semiconductor chip, connecting each first terminal to a selected second terminal located on a second surface of the semiconductor chip where each selected second terminal is not aligned with the first terminal to which it is connected, and generating an internal signal based on a selected one of the received selection signals.

Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Abstract: A lead frame includes a die pad and a plurality of leads arranged around the die pad. Each of the leads includes an inner lead, a bent portion, and an external connection terminal. The inner lead includes a distal portion, adjacent to the die pad, and a connection end portion, located at an opposite end of the inner lead from the distal portion. The bent portion is connected to the connection end portion of the inner lead. The external connection terminal is connected by the bent portion to the connection end portion of the inner lead and located below the inner lead. The external connection terminal includes an upper surface that faces to and is parallel to a lower surface of the inner lead. The inner lead, the bent portion, and the external connection terminal are formed integrally in each of the leads.

Abstract: An electronic package structure includes a substrate having a plurality of conductive leads. A discharge hole is disposed to extend through the substrate. An electronic chip is electrically connected to the plurality of conductive leads. A case is connected to the substrate and defines a cavity between the substrate and an upper of the case. The discharge hole and the electronic chip are disposed within the cavity, and the discharge hole is open to the outside in the electronic package structure. The discharge hole is configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the electronic package structure.

Abstract: A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided.

Abstract: A semiconductor device includes a semiconductor chip including first to fourth pads, and first and second switches. The first switch includes first and second nodes coupled to the first and second pads and sends from the second node a current larger than a threshold flowing in from the first node. The second switch includes third and fourth nodes coupled to the third and fourth pads and sends from the fourth node a current larger than a threshold flowing in from the third node. The third and fourth nodes are not coupled to any nodes of high and low potentials of any circuit which receives the potentials to operate. A first wire is coupled to the first pad and the first conductor, and a second wire is coupled to the second pad and the second conductor.

Abstract: Memory devices with controllers under stacks of memory packages and associated systems and methods are disclosed herein. In one embodiment, a memory device is configured to couple to a host and can include a substrate, a stack of memory packages, and a controller positioned between the stack and the substrate. The controller can manage data stored by the memory packages based on commands from the host.

Abstract: A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding compound layer on the first package substrate. The upper package includes a second package substrate and at least one upper semiconductor chip on the second package substrate. A heat transfer member includes a first portion disposed between the interposer and the upper package, a second portion disposed in the at least one opening of the interposer, and a third portion disposed between the interposer and the lower package.

Abstract: The present invention provides a bonding method in semiconductor manufacturing process and a bonding structure formed using the same, which can achieve wafer-level bonding under a condition of normal temperature and low pressure. The bonding method comprises generating bonding structures capable of being mutually mechanical interlocked, wherein the frictional heat generated by the bonding structures capable of being mutually mechanical interlocked is higher than the bonding energy therebetween, and utilizing the frictional heat generated by the bonding structures capable of being mutually mechanical interlocked to bond the bonding structures capable of being mutually mechanical interlocked.

Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

Abstract: A semiconductor device includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer and a second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit.

Abstract: A flexible substrate may have one or more bends. A bend in a flexible substrate may be made along a bend axis. Conductive traces in the flexible substrate may have elongated shapes. Each conductive trace may extend along a longitudinal axis that is perpendicular to the bend axis. Metal or other conductive materials may form the conductive traces. The traces may be formed from a chain of linked segments. Each segment may have patterned trace portions that surround one, two, or more than two openings. Traces may also be formed that have multiple layers of metal or other conductive material interconnected using vias. A polymer layer may cover the traces to align a neutral stress plane with the traces and to serve as a moisture barrier layer.

Abstract: An electronic apparatus includes a display device, a carrier structure, an electronic device, a sensing unit and a control unit. The carrier structure is electrically connected to the display device. The electronic device is selectively carried on the carrier structure and electrically connected to the display device through the carrier structure. A tilting angle of the electronic device changes with an actuation of the carrier structure. The electronic device has a first display surface. The display device has a second display surface. The sensing unit is disposed at the carrier structure or the electronic device and adapted for sensing the tilting angle. The control unit is disposed in the electronic device and electrically connected to the sensing unit. The control unit is adapted for determining a relationship between an image displayed by the first display surface and an image displayed by the second display surface according to the tilting angle.

Abstract: An organic light emitting display includes a data driving unit connected to data lines, a scan driving unit connected to scan lines, and a display panel having pixel groups arranged in a region where the data lines and scan lines intersect. A pixel group includes a first pixel unit having a first organic light emitting diode configured to emit light of a first color and a second pixel unit having a second organic light emitting diode configured to emit light of second color. The first pixel unit further includes an organic light emitting diode configured to emit light of a third color and the second pixel unit further includes an organic light emitting diode configured to emit light of the third color.