Abstract: A method of transferring update data from a microcomputer to a memory device having a transportable non-volatile memory median requiring that the transportable non-volatile memory median is divided into a plurality of sectors. Update data is to be written to data sectors of the transportable non-volatile memory median in accordance with a sector map. One of the sectors to be updated is the directory sector and another one of the sectors to be updated is the file access table sector. The microcomputer is programmed to reserve a specified number of sectors as a recovery area wherein some of the sectors of the recovery area are reserved for the sector map and other sectors of the recovery area are reserved for storage of the update data. The microcomputer identifies if a sector map resides in the recovery area. If no sector map resides in the sector map area of the recovery area, the microcomputer proceeds to identify which of the sectors are to be updated and generating a sector map accordingly.

Abstract: A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices.

Abstract: A gateway system for connecting first and second communication networks has first and second network end nodes and a protocol converter. The gateway system operates to provide input-output services of both network protocols to users of both networks in communicating through the gateway system. The gateway system employs associated complement protocol circuits in the end nodes and the protocol converter to provide these services. An efficient technique for generating the complement protocol of a first network is to prune finite state machines representing the operation of the second network protocol to provide the services of the second protocol that are not provided by the first protocol. The complement protocol circuits for the second network are then constructed based on the pruned finite state machines representing the operation of the first protocol.

Abstract: An apparatus and method are disclosed for supporting a plurality of outstanding requests between a client and server in a network. If the server completes computation of a later request from a client before an earlier request, then the network protocol supports transmission of responses in an out-of-order manner to the client, thereby allowing a high degree of parallelism on the client and the server. The server buffers responses until receiving an implicit acknowledgement from the client.

Abstract: A digital signal processor having a multiplierless computation block (140) is accomplished by storing approximations of computed logarithms in memory (160, 162). When two pieces of data (114, 116) are received, the approximate logarithms, or logarithmic data (120, 128), for each of the pieces data are retrieved from memory. The logarithmic data (120, 128) is them summed to produce a resultant (136), wherein the resultant (136) is used to retrieve an inverse logarithmic approximation (180) that is stored in memory (170, 172) in a manner similar to that of the logarithmic approximations. The inverse logarithmic approximation (180) that results closely approximates the product of multiplying, or another arithmetic function, the two pieces of data (114, 116).

Abstract: According to the present invention, a 3D connectivity-conserved grain-structured processing architecture uses connectable massively parallel processors. A 3D grain-structured processing architecture is provided. The 3D links of the grain-structured processing architecture provide direct local communication as well as global communication for voxel processing and analysis tasks. A novel transport naming scheme which is scalable in any three-dimension direction and the local/global communication protocol are disclosed. The 3D volumetric data set is first divided into a set of voxel sub-cubes. Each voxel subcube is processed by a processor element of the grain-structured processing architecture. Data discontinuity is produced after performing local operations in a massively parallel processors environment and requires replacing the resulted voxel data set in the overlap region for each voxel sub-cube.

Abstract: A novel quantum dot-tunnel device having a revolutionarily faster processing speed and higher processing precision than conventional computer computation, which device has an array consisting of a large number of quantum dots which confine electrons three-dimensionally, with the coupling among quantum dots, that is, the tunnel transition probability, being defined by controlling the positional relationship and the shape of the quantum dots in accordance with an algorithm of predetermined information processing, so that the algorithm is expressed in solid state rather than by a conventional computer program. The electron transition among quantum dots occurs instantaneously and wave mechanically with a strict precision, and the results of the information processing are expressed as a spatial distribution of electrons over the plurality of quantum dots.

Abstract: A method for interconnecting and operating in parallel a number of autonomous data processors each having a data memory, an instruction memory and a communication interface includes, before beginning a data processing sequence, loading memories of the autonomous data processors with individual algorithms, data sets and protocol instructions. A hardware communication system common to all of the autonomous data processors is connected to communicate with the communication interfaces of all of the data processors to regulate operation of the data processors. The communication system is programmed with an overriding body of execution sequence commands for the data processors to initiate and sequence autonomous processing of data in the data processors.

Abstract: A method and apparatus for identifying at least a portion of a framing pattern in a data stream comprising a plurality of sequential bits. In the method embodiment, the method includes the step of identifying a set of successive candidate bits wherein the identified candidate bits are spaced apart from one another. The successive candidate bits include a first candidate bit, a last candidate bit, and a predetermined number of intermediary bits between the first candidate bit and the last candidate bit. Each of the intermediary bits has a numeric relative position between the first candidate bit and the last candidate bit. The method further includes the step of identifying a group of look ahead bits corresponding to each of the intermediary bits. Each of the groups has a number of look ahead bits, and the particular number of such bit for a given group equals the magnitude of the numeric relative position for the intermediary bit corresponding to the group.

Abstract: A match bus operation circuit is disclosed for detecting load/store conflicts created by out-of-order instruction execution in a superscalar microprocessor having first and second busses. A ratio logic compare circuit generates a match bus indicating a match or conflict between the first and second busses. A ratio logic priority circuit is coupled to the ratio logic compare circuit for receiving the match bus and generating a priority bus indicating a first match of the match bus. A ratio logic mask circuit is also coupled to the ratio logic compare circuit for receiving the match bus and generating a mask bus that flags all instructions after the first match for discarding. A ratio logic multiple hit circuit is also coupled to the ratio logic compare circuit and indicates whether more than one instruction has matched.

Abstract: A method and apparatus for enhancing the capability of office machines, namely fax machines, includes coupling the office machine to a personal computer and enabling the office machine to access enhanced features supported in the personal computer. After identifying whether the personal computer is available and determining the capabilities it supports, the office machine can operate in an enhanced mode using the resources of the personal computer and can advertise its enhanced capabilities to other machines. The office machine still retains its ability to operate stand-alone mode if the personal computer is not available.

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

Abstract: A microprocessor execution unit includes an arithmetic unit and an addressing unit. The arithmetic unit performs arithmetic and logical operations on operands. The addressing unit operates in conjunction with the arithmetic unit to calculate offsets, limits, and linear addresses in a single cycle.

Abstract: An apparatus and methods are provided for pre-compressing data to be sent to a peripheral device in a computer system, sending the data to the peripheral device as a compressed data stream, and decompressing the data for use in the peripheral device in a real-time format. In a preferred embodiment, a unique peripheral device controller is provided having a data handling and decompression pipeline for receiving and decompressing an incoming compressed data stream in concert with a state machine for sensing the states of elements of the peripheral device, and for providing the decompressed data stream to data-using elements of the peripheral device. The peripheral device can be any device for which large amounts of data are typically needed, including, but not limited to printers, video displays, robotic driving devices, and data recording and media writing devices. Alternative methods are disclosed for compressing and decompressing data in systems according to the invention.

Abstract: A PCMCIA card includes a support, circuit components for providing faxmodem functions with respect to the support, a housing containing at least part of the support, a retractable cord mechanism at least partly contained in the housing for connecting the electronic component with an external device for communications therewith, the retractable cord mechanism including a cord and a storage mechanism for storing at least part of the cord in the housing, and a connector coupled to the cord for connecting to the external device. Alternate embodiments use optical or radio signal coupling from the PCMCIA card and all embodiments do not require a separate telephone connector to a telephone wall jack.

Abstract: A method is provided for parallel and cooperative processing of data in a system wherein a coordinator process cooperates with one or more agent processes to which portions of the data processing function is off loaded. The agent processes read and process the data and accumulate a partial result. Each agent process, responsive to statistics collected on the content of the data processed, returns a partial result of the processing to the coordinator process. These steps are repeated iteratively until the processing has been completed. In a specific application, the performance of data processing systems is improved by speeding up database group-by queries. The group-by operation processing is distributed between the host central processing unit (CPU) and the input/output (I/O) processors (IOPs). Essentially, the IOPs are sent group-by requests to be performed on a set of disk blocks (extents), along with a predicate for tuples to be selected for query.

Abstract: A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.

Abstract: A medical transaction system is disclosed which is capable of permitting a plurality of healthcare providers to communicate with a plurality of payors and financial institutions. The healthcare providers, payors, and financial institutions do not have to communicate in the same data message formats nor in the same communication protocols. Such a system facilitates not only the processing of medical claims submitted by the healthcare providers to the payors, but also permits the transfer of medical data records between healthcare providers. The system supports the processing of medical claims without requiring a centralized database or imposing a uniform claim format on the healthcare providers and payors. The preferred embodiment of the invention further includes a financial transactor that uses remittance information from the payors to generate the electronics funds transfer messages to credit and debit accounts.

Abstract: An information processing system includes processors grouped in nodes (1) associated with one another by links (4) in a variable number of nodes up to the maximum configuration, which is divided into subsets (3) having a critical size relative to a rate of messages between nodes, the nodes in one subset being connected to one another by double serial links, and the nodes of two adjacent subsets being connected by single serial links, the nodes preferably being grouped in two supernodes including two subsets (3).

Abstract: An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.