Abstract: Method, system, and apparatus are described for automatically receiving, at an intermediate processing location, data from a wide variety of remote sources, identifying the format of the data, translating the data to a common file format, sending the data to a recipient in an intermediate format, then translating the data to the specific format needed by the particular recipient. The system operates automatically with little human intervention. A unique system for automatically selecting and implementing specific translation modules is also described. Error checking features ensure that the transferred data matches the original data although the format is altered, and documentary receipts are sent to each section of the system that sends data, and logical, statistical and mathematical operations may be performed on the data.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package.

Abstract: A mask programmable register (40) determines a default configuration of a data processor during a reset operation. The default configuration is driven to a plurality of external integrated circuit pins (48) of the data processor with weak drivers (528, 534, 540, 546). Then, on an individual pin basis, an external user (11) may choose to allow each integrated circuit pin to remain in a default state or be drive with an external configuration value. When the external user chooses to allow the integrated circuit pin to remain in the default state, an internal default configuration data value provided by the internal mask programmable register is output by the integrated circuit pin. Conversely, when the external user chooses to override the default state, the user may drive the external configuration value to the integrated circuit pin using an external data source.

Abstract: A communication system using a network route establishing technique for a network having a plurality of nodes connected through links, in which a route search message is delivered simultaneously in a plurality of directions from a sender node through a network route to a destination node, and a confirmation is delivered from the destination through the network route back to the sender node, and accordingly, a network route is established. The communication system includes a device for detecting, at a node through which a search message is to be transmitted, a possibility of a transmission of the search message beyond the node, a device for delivering a cancel message in the direction from which the search message has been transmitted, and a device for releasing the network route engaged by the search message, based on the delivered cancel message.

Abstract: The present invention relates to a method of search in which a plurality of candidate of character strings likely to coincide with a designated key word are detected from a text character string, and it is decided whether the candidate character strings detected include a character string coincident with the key word character string. Further, the sequence of detection of character string candidates is determined in such a manner that a portion having a succession of characters coincident with any of a plurality of characters included in the key word character string is selected as a candidate character string.

Abstract: A microprocessor with a bus sizing function has internal data bus and external data bus having 2.sup.n bit width, in which n is a natural number, for inputting and outputting data to and from said data path, 2.sup.n interface circuits having a bus sizing function for using as a bus of 2.sup.m bits, in which m is a natural number smaller than n, said interface circuit being connected to 2.sup.n-m of internal data buses and 2.sup.n pads for connecting said internal data bus to the external data bus via said interface circuit. Among said interface circuit and said pads, 2.sup.n-m of said interface circuits and said pads associated with common internal data bus are aggregated as a block and arranged at close proximity to each other.

Abstract: A data ordering system for use with personal computers having data pipelining capability is disclosed. The personal computer comprises a central processing unit (CPU) which issues data requests to one or more data exchange units, such as memory units or data Input/Output units. The data ordering system comprises a finite state machine (FSM) which receives inputs indicative of data requests transmitted by a central processing unit (CPU). The inputs cause the FSM to assume different output states which are indicative of the proper order of data requests. The state outputs of the FSM are used to enable or disable the transmission of data between the data exchange units and the CPU in order to insure the proper order of data responses to the issued data requests.

Abstract: A method and system are disclosed for reading data from an m-byte memory device utilizing a processor having an n-byte data bus, where m is less than or equal to n, which do not require the processor to support special bus cycles, bus select signals, or dynamic bus sizing. Responsive to an initiating signal from the processor to an interface controller, a plurality of data latches are initialized by a control signal. An address counter is also initialized. The memory device is activated by a control signal. Latching of data by one of the plurality of data latches is enabled. Data associated with an address indicated by the address counter is then latched from the memory device utilizing the enabled data latch. The address counter is incremented. The enabling, latching, and incrementing steps are repeated until n bytes of data are latched. When n bytes of data are latched, the processor is signaled that n bytes of data are valid to read.

Abstract: A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65), a plurality of edge interface circuits (14,16), and a bus interface controller (22). In an alternate embodiment, multiprocessor data processing system (210) includes an array (212) of data processors (250-258), a plurality of edge interface circuits (214-217), and a bus interface controller (222). The data processing systems (10,210) are capable of performing complex data movement patterns between the processors (50-65,250-258) and the corresponding edge interface circuits (14, 16, 214-217), such as a transpose pattern, a ping-pong pattern, and a checkerboard pattern.

Abstract: A vector processing device includes a vector unit having operation pipelines and a vector register connected to the operation pipelines, a memory unit to be operated by the operation pipelines and results of operations obtained from the operation pipelines, and a memory control unit having a data buffer provided between the vector register and the memory unit. The vector processing device also includes data buffer valid counter counting the number of pieces of data read from the vector register and sent to the data buffer, and pipeline stop predictor selectively interrupting outputting an access request from the vector unit to the memory unit on the basis of the number of pieces of data counted by the data buffer valid counter when the operation pipelines are chained via the vector register.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A reset intercept circuit is provided on the non-volatile memory die for intercepting the signal which is provided to the reset input of the non-volatile memory die from external of the multi chip package. The reset intercept circuit provides a modified version thereof to the processor die. Particularly, the reset intercept circuit performs the function of sending a modified version of the reset signal to the processor die responsive to the present mode of operation of the multi chip package at the time the reset signal is received.

Abstract: An adapter arrangement for internetworking a non-CTOS computer means with a network of CTOS terminals, including a system-bus, this arrangement being adapted for introduction into, and cooperation with, the non-CTOS computer and comprising CTOS-net bus means for transferring signals from the system-bus plus a communication control stage for controlling and transferring signals to/from the CTOS network and a net-interface stage.

Abstract: A microcontroller which directly drives a memory with low order address bits during a fetch operation. Driving the low order address bits directly while the high order bits are latched during an address/data multiplex on the same pins allows the latch enable cycle to be skipped during sequential fetches. A sequential address detector indicates when the latch enable cycle can be skipped.

Abstract: A technique to facilitate decryption processing of information packets transmitted over a communication network after encryption in accordance with a specific network protocol, the details of which may be subject to later change as standards are developed or modified. Programmable registers are used in the decryption process to hold information for identifying an incoming information packet as being subject to the specific protocol and requiring decryption, and identifying a starting location of a data field to be decrypted. Specifically one programmable register contains a first offset locating an identifier field in the packet, in which a cryptographic identifier will be found if the packet is one conforming to the protocol; another programmable register contains a cryptographic identifier value that will be found in the identifier field if decryption is to be performed, and a third programmable register contains a second offset to locate the beginning of a data field to be decrypted.

Abstract: A system and method for preprocessing and delivering multimedia presentations to customers such that delays due to interactive response time is virtually eliminated include a preprocessor, mass storage, a delivery processor, a distribution network, and a plurality of presentation processors. The preprocessor receives as inputs an original multimedia presentation and parameters characterizing other system components, which parameters include the round trip latency between the delivery processor and a presentation processor, and generates a preprocessed multimedia presentation including a delivery schedule in the form of a labelled, directed graph.

Abstract: In an information processing system having plural processing units connected through a communication medium, each processing unit operates to receive information to be transmitted from a processing portion operating in the processing unit to the communication medium and a content code predetermined according to the content of the information to be transmitted. Based on the received content code, the processing unit operates to determine an address of the destination processing unit, a sending mode used for transmitting the information, and whether or not the more reliable communication method arranged to establish a connection between the processing units is used for transmitting the information. Then, by using the sending mode and the communication method obtained as the determined result, the information is transmitted to the processing unit having an address obtained as the result determined through the communication medium.

Abstract: A data processing system (10) includes a register bit structure (27) which can be hard-wired (37, 39) but is also selectively configureable for read/write operation.

Abstract: DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory.

Abstract: A method and apparatus for generating status information about a pipelined processor after the completion of an execution of an instruction. A first storage device stores the current overall status of the processor due to the execution of a plurality of instructions previous to the presently executing instruction. A second storage device stores an instruction status which represents the status of the processor due to the presently executing instruction alone. Logic generates a new overall status which represents the staus of the processor due to the execution of the present instruction and the previous instructions wherein the new overall status is generated from the instruction status and the current overall status.

Abstract: An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.