Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: Cross-coupled charge-pumps. At least some of the example embodiment are methods including: pumping charge from a first capacitor through a first field effect transistor (FET) to a voltage output and from a second capacitor through a second FET to the voltage output of the charge pump; refreshing charge to a third capacitor and a fourth capacitor during the pumping of charge; electrically isolating the first through fourth capacitors during a dead time; and then pumping charge from the third capacitor through a third FET to the voltage output and from the fourth capacitor through a fourth FET to the voltage output of the charge pump; and refreshing charge to the first capacitor and the second capacitor during the pumping of charge from the third and fourth capacitors.

Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

Abstract: Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a signal generation component that implements a control sequence that comprises a single pulse type for a first quantum bit and at least a second quantum bit of a quantum circuit. The computer-executable components can also comprise a coordination component that synchronizes a first pulse of a first channel of the first quantum bit and at least a second pulse of at least a second channel of the second quantum bit. The coordination component can simultaneously apply the first pulse to the first quantum bit and at least the second pulse to at least the second quantum bit.

Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature s

Abstract: A high power semiconductor switch including a plurality of transistor switch circuits connected in series between first and second ports. A first set of transistor switch circuits is located immediately adjacent to the first port, a second set of transistor switch circuits is located immediately adjacent to the second port, and a third set of transistor switch structures are located between the first and second sets. Each transistor switch circuit of the first and second set includes a switching transistor and a dynamic impedance circuit, wherein the dynamic impedance circuit reduces the effective impedance of the corresponding switching transistor when an RF signal is being transmitted. The dynamic impedance circuits are designed to reduce and equalize the voltage drops across the switching transistors of the first and second sets.

Abstract: A system for monitoring pulse width modulation (PWM) duty operation execution for motor control, which can detect whether or not the PWM duty operation execution used for torque and speed control of a motor is performed normally within an interrupt execution timing, and perform failure diagnosis depending upon the detected result, thus enhancing stability of motor control.

Abstract: The de-Qing loss and phase imbalance caused by the inherent capacitance of a switched resistance, such as a MOSFET with a resistor, can be reduced by using a shunting switch across the resistor that is in series with the resistor's switch. The shunting switch shorts across the resistor when the resistor's switch is open and in reference mode, thereby significantly reducing the resistance in series with the inherent capacitance of the open resistor's switch.

Abstract: An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal.

Abstract: A semiconductor apparatus includes an internal clock generation circuit, a receiver, and a sampling circuit. The internal clock generation circuit generates a receiving clock signal and a sampling clock signal based on a reference clock signal, the sampling clock signal having a phase different from the receiving clock signal. The receiver receives an input signal in synchronization with the receiving clock signal and to generate an amplified signal. The sampling circuit samples the amplified signal in synchronization with the sampling clock signal to generate an output signal.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.

Abstract: Detecting the health of a phase-lock loop (PLL) generating a feedback clock signal based on a reference clock signal, includes providing, by a delay line, the feedback clock signal to a plurality of latches clocked by the reference clock signal; providing, based on an output of the plurality of latches, an input to a plurality of sticky latches, the input indicating whether an edge of the feedback clock signal was detected; determining, based on a number of asserted sticky latches of the plurality of sticky latches, a phase error metric; comparing the phase error metric to a threshold; and outputting, based on the comparison, an indication of a lock state.

Abstract: An embodiment of the present invention relates to a coil assembly for a wireless power transmitter, comprising: a single coil, which comprises a wire, and which has a circular hole formed therein; and a plurality of shielding members (ferrites) coupled to the single coil, wherein the outer diameter of the single coil may be approximately equal to or larger than about 185 mm and equal to or less than 195 mm, and the inner diameter of the single coil may be approximately equal to or larger than 75 mm and equal to or less than 85 mm.

Abstract: A plurality of gate driver units (3,4) respectively drives a plurality of semiconductor switching devices (SW1,SW2) connected in parallel. A control circuit (5) controls the plurality of gate driver units (3,4). Each gate driver unit (3,4) includes a gate driver (6) supplying a gate voltage to a gate of the corresponding semiconductor switching device (SW1,SW2), and a potential difference measuring unit (7) measuring a potential difference (Va) arising due to wiring inductance on an emitter side of the corresponding semiconductor switching device (SW1,SW2) for each cycle of an output frequency. The control circuit (5) adjusts the gate voltage (VGE) supplied by the gate driver (6) of each gate driver unit (3,4) such that the potential differences (Va) of the plurality of semiconductor switching devices (SW1,SW2) in turn-on or turn-off switching operation become same as each other.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.