Abstract: A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer.

Abstract: A semiconductor light emitting element with a high light-emitting efficiency, which is constituted in such a way that, of the composition of its GaN and AlN epitaxial layer, part of N is substituted by P, thus ensuring good lattice-matching with the substrate crystal, ZnO.

Abstract: An IC card comprises a card board having first and second major surfaces and a semiconductor module having an electrode terminal face. The semiconductor module is mounted in the card board, so that the electrode terminal face is exposed onto the first major surface of the card board. The card board comprises a board frame and a resin which is molded inside the board frame. Part of the semiconductor module surface which is opposite to the electrode terminal face, is covered with the resin.

Abstract: An adjustable CCD gate structure utilizing ultra-violet light activated floating gates, wherein a floating polysilicon gate is used between a CCD electrode and the underlying substrate to provide a fixed voltage bias to the CCD gate during the manufacturing process thereof The floating gate is programmed with a desired voltage bias during the application of ultra-violet light and is thereafter fixed at that adjusted level, upon the removal of the ultra-violet light.

Abstract: A dielectrically isolated island architecture in which the island is contoured inwardly to form one or more projections that penetrate a well separating two regions in the island to assure that the two regions will be electrically isolated without additional processing steps.

Abstract: A pyroelectric IR-sensor in which a pyroelectric light receiving element is mounted on a MID substrate or a ceramic substrate having a thermal conductivity less than 0.02 cal/cm.multidot.sec.multidot..degree.C. Both ends of the pyroelectric light receiving element are supported by the substrate, with the central portion of the pyroelectric light receiving element being spaced from the substrate. Chip parts are mounted on the substrate.

Abstract: A compound semiconductor device wherein a contact to an n type Al.sub.x Ga.sub.1-x As layer comprises an In.sub.x Ga.sub.1-x As graded-composition layer, an In.sub.x Ga.sub.1-x As contact layer having a constant composition and a metal electrode layer, the In.sub.x Ga.sub.1-x As graded-composition layer is doped with an n type impurity which concentration is higher than a concentration of an impurity activated as n type, whereby, even when a thickness of the In.sub.x Ga.sub.1-x As graded-composition layer is made sufficiently small, a reduction in the carrier concentration of the thin graded-composition layer causes no increase of its resistance and a low-resistance contact is realized.

Abstract: According to the present invention, the hetero junction bipolar transistor (HBT) is provided which includes an emitter layer consisting of a first semiconductor of a first conductive type and being in mesa form; a base layer being in contact with the emitter layer and consisting of a second semiconductor of a second conductive type having a narrower band gap than the first semiconductor; and a collector layer being in contact with the base layer and consisting of a third semiconductor of a first conductive type having a broader band gap than the second semiconductor. In this HBT, a monolayer sulfur film is formed so as to cover the exposed periphery of the heterointerface between the emitter layer and the base layer.

Abstract: Technology for using a wiring of a superconductive material in semiconductor integrated circuit device. An isolation layer and/or a barrier layer are provided for preventing diffusion of harmful composition of the superconductive material for the semiconductor device. Control of a circuit can be made utilizing the characteristics of a superconductive material. Also, the characteristics of a superconductive material may be controlled. A method of forming a layer of superconductive material, well compatible with the widely used process of manufacturing integrated circuit devices, is also disclosed.

Abstract: A distributed threshold voltage TFT has a first FET and a second FET connected in series with the first point between the first and the second FET via a series circuit of a first capacitance and a second capacitance. The gate of the second FET is connected to the junction point between the first and the second capacitance and to the gate of the first FET via a non-linear resistance with a low R.sub.on and a high R.sup.off. Leakage currents can be kept very low in this DTV FET without an extra external voltage and/or without extra doping.

Abstract: A submicron-width fuse element is disclosed that protects peripheral DRAM chip devices from low current failures below the range of metal fuse elements. In a specific application, the fuse elements are used to protect a DRAM chip from dielectric failure of voltage supply filtering capacitors. A low cross-section and length allows minimum space for the element.

Abstract: The line material is of a laminated structure consisting of: a Ta containing N alloy layer (lower layer) which is a first metal layer made of at least an alloy selected from the group consisting of a TaN alloy, a Ta-Mo-N alloy, a Ta-Nb-N alloy and a Ta-W-N alloy; a second metal layer (upper layer) formed integrally with the first metal layer and made of at least an alloy selected from the group consisting of Ta, a Ta-Mo alloy, a Ta-Nb alloy, a Ta-W alloy, a TaN alloy, a Ta-Mo-N alloy, a Ta-Nb-N alloy and a Ta-W-N alloy; and/or a pin hole-free oxide film. The line material of the laminated structure is to be applied to the formation of signal lines and electrodes of, e.g., a liquid crystal display. The line material has a low resistance and the insulating film formed by anodization and the like exhibits excellent insulation and thermal stability. Therefore, when the line material is applied to signal lines of various devices, it exhibits excellent characteristics.

Abstract: A thin-film electroluminescence device has transparent electrodes formed on a transparent substrate, a lower dielectric layer formed on the substrate having the transparent electrodes, a luminescent layer formed on the lower dielectric layer, an upper dielectric layer formed on the luminescent layer, and back electrodes formed on the upper dielectric layer. At least one of the upper and lower dielectric layers includes a SiN:H film formed in contact with the luminescent layer by a plasma chemical vapor deposition method. The SiN:H film contains N--H bonds of 1.2.times.10.sup.22 /cm.sup.3 or less to control an amount of change in emission-start voltage to 30 V or less.

Abstract: A DRAM cell having a tunnel-shaped structure (in the form of buried bit line structure) and a formation process therefore are disclosed. A storage poly and a local connecting layer are interconnected in such a manner as to form a tunnel-shaped portion, and a bit line passes through the tunnel formed by the combination of the local connecting layer and the storage poly. A flattening insulating layer, a bit line capping-oxide-layer and a spacer are filled between the storage poly, the local connecting layer and the bit line. The storage poly is contacted through the local connecting layer to a first semiconductor region, while the bit line is directly contacted to a second semiconductor region.

Abstract: Epoxy bonding between an IC chip and a chip carrier is strengthened by creating substantially rougher oxidized surfaces within substantially smooth gold surfaces of a die paddle portion of the chip carrier.

Abstract: A process for formation of an LDD transistor and a structure thereof are disclosed in which the junction capacitance and the body effect can be properly reduced. In the conventional LDD transistors, the punch-through problem is serious, and in the improved conventional LDD transistor also, there is a limit in increaseing the channel concentration, as well as the body effect being increased. The present invention gives solutions to the above problems by arranging that the junction thicknesses of n.sup.+ source and drain become smaller than the junction thicknesses of n.sup.- regions, and that a p type pocket 6 be formed only near a gate and a p type pocket 6.

Abstract: Disclosed is a semiconductor device incorporating a plurality of photodiodes and comprising a prism on the device surface. A first and a second optical film are deposited on the surface of a first photodiode. Furthermore, the first optical film is formed on the surface of a second photodiode, and the second optical film is provided at the periphery of the photodiode. This structure securely protects the pn junction of the second photodiode during manufacture. In addition, a light-shielding metal film formed at the periphery of the photodiodes has an insulation film deposited thereon, the insulation film containing very low stress and providing high adhesiveness with respect to the prism. This arrangement enhances the reliability of the semiconductor device.

Abstract: There is disclosed a solid-state image sensor comprising: photo-detecting devices arranged in a matrix structure for receiving external light signals; vertical charge transfer device interposed between the columns of said photo-detecting device for vertically transferring the charges produced from said photo-detecting device according to external control signal; first horizontal charge transfer device for horizontally transferring the charges coming out of said vertical charge transfer device according to external control signal; output control device for controlling the charges flowing from said first horizontal charge transfer device to said output device; second horizontal charge transfer device for transferring the output charges of said first horizontal charge transfer device controlled by said output control device to said vertical charge transfer device according to external control signal; and a feedback line for connecting the output of said first horizontal charge transfer device to the input of sai

Abstract: The present invention, which is directed to a light-emitting diode array for use as the light source in optical printers and other such applications, provides improved optical efficiency and a more uniform distribution of emission intensity. The light-emitting diodes are formed as reverse mesas with a mirrored sloping surface that reflects light in the direction of the light emitting surface of the diode. This improves the emission efficiency of each diode. In addition, this also increases the light output from the edge portions of light-emitting surfaces of the diodes so as to produce a more uniform distribution of light output from the light-emitting diodes.

Abstract: A composite flip chip semiconductor device (10) permits burn-in testing and rework to be performed on the device while also enhancing electrical, thermal, and mechanical device performance. The device includes a semiconductor die (12) having a plurality of bonding pads (14). Also included in the composite device is an interposer (22) having a first surface with a plurality of traces (26). A plurality of vias (24) extend from the first surface of the interposer (22) to a second surface. The semiconductor die (12) is electrically coupled to the plurality of vias of the interposer which in turn is to be coupled to a substrate.