Abstract: A reverse bias current supply system for a switching device having a circuit including a constant voltage device connected in parallel with an electrical circuit which supplies a base reverse bias current to the switching semiconductor device so that a voltage across the electrical circuit is clamped to control the base reverse bias current at a constant level regardless of variations in the power supply or component characteristics.

Abstract: A driver circuit is provided which includes a field effect transistor having first and second spaced apart semiconductor regions of a given conductivity type and a third semiconductor region of a conductivity type opposite to the given conductivity type interposed between the first and second regions and having a given sustaining voltage serially connected with a capacitor. The circuit further includes means for applying between the first and second spaced apart regions a given supply voltage having a magnitude greater than the magnitude of the sustaining voltage and less than the breakdown voltage of a PN junction formed in the transistor and means including a control voltage applied to the gate electrode of the transistor for initiating current flow between the first and second spaced apart regions when the given supply voltage is applied between the first and second spaced apart regions.

Abstract: An arrangement for suppressing amplitude variation in FM signals comprises a frequency divider which frequency divides an incoming FM signal to provide frequency divided signals having two discrete levels dependent upon the amplitude of the incoming FM signal in relation to a threshold value, and a frequency multiplier which combines the frequency divided signal to provide an output signal of substantially constant amplitude and having a frequency equal to that of the incoming signal.

Abstract: A timing signal generator which can operate stably even when, or directly after, a power supply is switched on. The generator is of the type having a first dynamic delay circuit for generating a first timing signal in response to said input control signal and a second dynamic delay circuit for generating a second timing signal in response to the first timing signal, and is featured by a first transistor connected between the output of the first dynamic delay circuit and a voltage terminal with a gate connected to the input of the first dynamic delay circuit and a second transistor connected to the output of the second dynamic delay circuit and the voltage terminal with a gate connected to receive the first timing signal.

Abstract: An apparatus for selectively switching between either of two RF clock signal sources utilizes field effect transistors (FET's) as the switching elements. The FET's are driven at their respective base electrodes by complementary signals from open collector logic gates to provide signal source selection. In the event of loss of power to the RF switch, the energy from the RF signal passing through the previously selected switch path provides a positive (enabling) bias to the FET's in that path and a negative (disabling) bias to the FET's in the other path, thereby maintaining the selected path. The open collector logic gate circuits appear as open circuits when power is lost. During normal powered-on operation, the selection logic overrides the RF signal energy biasing circuits.

Abstract: The disclosure relates to a broad band coupling arrangement with coupling point switches in ECL technology, whereby a plurality of coupling point switches are formed by a corresponding plurality of linkage elements which are integrated on one chip. In order to reduce the power comsumption, a switching transistor is inserted in the operating voltage supply of each chip, said switching transistor only being conductive when at least one linkage element of the appertaining chip is selected. The disclosure can particularly be employed in the distribution of video signals.

Abstract: Generating a digital signal from the output of a numerically controlled oscillator and delaying certain transitions of the digital to produce an output digital signal having a generally 50% duty cycle and a frequency determined by a frequency select input to the numerically controlled oscillator.

Abstract: This invention pertains to a power FET control circuit which operates at higher switching frequencies for reducing the output voltage ripple. The control circuit provides two pulse control signals each shifted 180.degree. out of phase, each of such signals having a fixed frequency and a duty-cycle ratio which varies up to a maximum of 50%.

Abstract: A logarithmic amplifier circuit provides pole-zero compensation for improved stability and response time over 6-8 decades of input signal frequency. The amplifier circuit includes a first operational amplifier with a first feedback loop which includes a second, inverting operational amplifier in a second feedback loop. The compensated output signal is provided by the second operational amplifier with the log elements, i.e., resistors, and the compensating capacitors in each of the feedback loops having equal values so that each break point or pole is offset by a compensating break point or zero.

Abstract: The described circuit arrangement converts an alternating current signal into a binary signal when the level of the alternating current signal exceeds an initial threshold voltage. During the period of time in which the alternating current signal is delivered, the threshold voltage is reduced. If the level of the alternating current signal falls short of the reduced threshold voltage, then the delivery of the alternating current signal is interrupted and the threshold voltage is again increased to its initial value. This hysteresis during switch-on and switch-off of the binary signal results in either an error-free binary signal being supplied or no binary signal at all.

Abstract: The emitter of an input transistor (T.sub.1) of a Darlington transistor is connected to the base of an output transistor (T.sub.2). The collector of the input transistor (T.sub.1) is connected to the input of a current amplifier circuit comprising a third transistor (T.sub.3) arranged as a diode and having a first resistor (R.sub.1) arranged in its emitter circuit, and a fourth transistor (T.sub.4) having its base is connected to that of the third transistor (T.sub.3) and having a second resistor (R.sub.2) arranged in the emitter circuit. The collector of the fourth transistor (T.sub.4) is connected to the base of the output transistor (T.sub.2). The ratio between the resistance values of the first and the second resistors (R.sub.1, R.sub.2) is larger than the ratio between the emitter areas of the fourth and the third transistor (T.sub.4, T.sub.3). Thus, for small currents a low and for large currents a high current gain is obtained, so that the current gain factor of the output transistor (T.sub.

Abstract: A circuit (40) is capable of receiving a very high voltage input signal, for example from a piezoelectric transducer (1). The circuit accepts the relatively large input voltage of the piezoelectric transducer (1) and provides an output signal proportional to the square root of the input voltage.

Abstract: An integrated circuit amplifier for a high impedance microphone (100) of the capacitance type is disclosed. The subject amplifier circuit permits the further miniaturization of an electret microphone as it is capable of providing an input impedance simulating a resistor value of hundreds of megohms. The circuit particularly comprises duplicate coupling circuits (101a and 101b), a source of reference direct current voltage (103), and a gain providing circuit (102). The coupling circuits (101a and 101b) comprise a first pair of diodes (Q1 and Q2) symmetrically placed about one input terminal (IN1) of the microphone (100). Outputs of the reference voltage source (103) are provided to coupling circuits (101a and 101b) and through the coupling circuits to gain providing circuit 102. Such an arrangement facilitates power supply noise rejection and automatic canceling of direct current voltage drifts.

Abstract: A Pockels cell driver using a microwave triode which transfers charge from a high voltage source to a Pockels cell via a storage capacitor. The microwave tube is controlled, through its grid voltage, by two pulse amplifiers each having a plurality of tandem field effect transistor (FET) stages so as to increase the voltage across the cell in two steps having a selected delay therebetween. The driver is especially useful for seeding and extracting output pulses from a regenerative laser amplifier having the Pockels cell within its cavity. The driver may be used to operate a Pockels cell as a switchout or shutter to select a single pulse from a pulse laser such as a mode-locked Q-switched laser.

Abstract: A digital signal delay circuit which delays a plurality of digital input signals by a use of a single delay device group and a plurality of delay sections is disclosed. The delay device group generates a plurality of different phase clock signals. Each of the delay sections includes selection means for selecting one of the clock signals from the delay device group and latch means for latching the digital input signal in response to the output signal from the selection means. The output signal from the latch means is the delayed input signal, and a delay time is controlled by the selection means. The delay device group is used in common for the plurality of delay sections, so that the digital signal delay circuit is simple and inexpensive in construction.

Abstract: An electrical circuit functioning as a temperature sensor which is fully compatible with silicon chip and similar integrated circuit technology. Four matched NPN bi-polar transistors provide a circuit that detects changes in temperature by monitoring the current throughput in operation. Environmental temperatures increase current approximately one order of magnitude for each 25 degrees centigrade of changing temperature. With a current gain of 100 for each transistor employed, the current increases from 0.1 microamp at 0 degrees centigrade to 11 microamps at 50 degrees centigrade.

Abstract: Apparatus for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, automatic de-skewing circuitry is provided on each of a plurality of clock distribution chips for de-skewing the clock outputs from different chips. In a preferred implementation of the de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Abstract: An LED driver circuit of a digital optical transmitter for an optical fiber data link includes a differential amplifier with emitter coupled transistors, an LED being connected to the collector of one of the emitter coupled transistors. A current source is connected to the common emitters to enable switching of the emitter coupled transistors in response to an input signal. The input signal, a first delayed input signal and a second delayed input signal, are applied to the current source through an OR circuit, to render the current source conductive in response to said input signal, the first delayed input signal or the second delayed input signal. The first delayed input signal and an inverted first delayed input signal switch the emitter coupled transistors when the current source is conductive. As the current source is conductive at the transistor switching times, high speed switching with smooth charging and discharging of the LED junction capacitance is achieved.

Abstract: A temperature compensated active resistor for use on an integrated circuit semiconductor chip is formed of a N-channel MOS transistor, a string of first, second and third transistors connected as a series of diodes, and a P-channel MOS transistor. The P-channel MOS transistor has its drain electrode connected to an output terminal in which a resistance value at the output terminal remains substantially constant over a relatively wide temperature range.

Abstract: A sensor-integrator circuit having a sensor for producing a current varying in accordance with the sensed parameter or a reference current source, a comparator having inverting and noninverting inputs and an output and charge storage device coupled to the inverting input. The circuit is energized to obtain a given positive steady state reset voltage, a reference voltage is applied to the noninverting input of a comparator which is less positive than the steady state voltage and integration is initiated solely by alternately applying the current from the sensor and the reference current to the inverting input of the comparator.