Patents Examined by Barry C. Bowser
  • Patent number: 5652526
    Abstract: An analyzer for performing high and low voltage tests on an electric induction machine having electric power input terminals.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: July 29, 1997
    Assignee: Southern California Edison Company
    Inventors: Kevin C. Sullivan, Manuel R. Cabison, Isidor Kerszenbaum, Juan P. Lopetrone, Tom Baker
  • Patent number: 5652506
    Abstract: An apparatus for measuring an a.c. current flowing in an electric cable comprises a pair of jaws for receiving the cable and which are movable towards one another to engage the opposite sides of the cable. A potentiometer generates a signal ("cable size signal") corresponding to the relative positions of the jaws. A set of coils is provided adjacent the jaws to detect the magnetic field generated by current flowing in the cable. A circuit in the housing is responsive to the cable size signal and the voltage induced in the coil for determining the amplitude of the current flowing in the cable and displaying the same on a display.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: July 29, 1997
    Inventors: Thomas Sorenson, Michael McCormack, Francis Keane, Eugene O'Doherty
  • Patent number: 5652507
    Abstract: The dynamic range of a current transformer (CT) is increased without reducing the scaling of measurements at the low end of the dynamic range by designing the core of the CT to saturate only after about 90 electrical degrees of the maximum current to be measured. The measurements taken during this first 90 electrical degrees before the core saturates are doubled to in effect add measurements representing the mirror image of the first 90 electrical degrees. Timing of the digitized samples taken during the first 90 electrical degrees is adjusted to account for core reset energy errors, by determining the rate of change of current just after a zero crossing and selecting an empirically determined value of current for timing the start of the measurement samples.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: July 29, 1997
    Assignee: Eaton Corporation
    Inventor: John Herman Blakely
  • Patent number: 5648728
    Abstract: An apparatus for positioning a workpiece comprises a plurality of pedestals each comprising a first portion having a first width, a second portion having a second width greater than the first width, and a chamfered portion interposed between the first and second portions. The inventive apparatus further comprises a support having a plurality of holes therein for receiving the plurality of pedestals, the support further having a plurality of chamfered portions with one the chamfered portion about a periphery of each the hole. A base urges the chamfered portions of the pedestal away from the chamfered portions of the support.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: July 15, 1997
    Assignee: Micron Electronics, Inc.
    Inventor: Robert L. Canella
  • Patent number: 5648725
    Abstract: A test instrument for testing magnet wire which is provided which tests, collects and permits analyzing the effect of temperature, frequency, voltage and rise time associated with magnet wire use, and more particularly, the effects of those variables on the insulation of the wire, so as to evaluate the magnet wire performance and inverter controlled dynamoelectric machine applications.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: July 15, 1997
    Assignee: Emerson Electric Co.
    Inventors: Vojislav V. Divljakovic, Joseph A. Kline
  • Patent number: 5646522
    Abstract: The wireless test fixture (50) for high frequency testing incorporates a printed wiring board (52) which directly interconnects the connector (55) into which a module (66) to be tested is inserted and the circuitry from a test machine (10) to minimize path lengths, minimize coupling between conductors, eliminate random coupling between wires and bundles, and eliminate most wiring.
    Type: Grant
    Filed: June 19, 1996
    Date of Patent: July 8, 1997
    Assignee: Hughes Electronics
    Inventors: Alan Etemadpour, Gary R. Haugh, Charles J. Lotka, Stephen Pizzica
  • Patent number: 5644249
    Abstract: This invention presents a method and a mechanism for contacting a set of vertical probes of a circuit testing mechanism with a set of pads or bumps of a circuit under test. The vertical probes have a circular cross section, a tip portion of length L1 and a beam portion of length L2, such that the beam portion extends at a right angle to the tip portion. The tip portion is guided through a guide hole to the pads of the circuit under test and the beam portion secured by its end. In this geometry the contact force between the probe and the pad is described by the relation: ##EQU1## where D.sub.v is a vertical deflection of the probe, I is an area moment of inertia of the probe about its axis, and E is a Young's modulus of the probe. The tip length L1 and beam length L2 are selected for each of the vertical probes in such a way the contact force F in this relation is kept constant thus ensuring that the contact force F between the vertical probes and pads remains substantially equal.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: July 1, 1997
    Assignee: Probe Technology
    Inventor: January Kister
  • Patent number: 5642055
    Abstract: A method and apparatus for electrically interconnecting various electronic elements, including circuit components, assemblies, and subassemblies. A particle enhanced material metal contact layer, having a surface, formed on the electronic elements, includes particles of greater hardness disposed on and/or within the metal contact layer, which particles form protuberances that concentrate stress when said contact surface is brought into contact with an opposing surface under pressure, to thereby penetrate the opposing surface and form a metal matrix between the two surfaces.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: June 24, 1997
    Assignee: Particle Interconnect, Inc.
    Inventor: Louis Difrancesco
  • Patent number: 5640102
    Abstract: The present invention provides a cost effective and compact pin test circuit for non-connection pins of the semiconductor device under test. The pin test circuit includes a plurality of exclusive DC channels each of which has a flirt relay controlled by a control signal for switching ON/OFF a power source which generates a predetermined voltage, and a second relay controlled by a control signal switching ON/OFF a fixed electric potential such as a ground level electric potential. The exclusive DC channel is used for the NC pin testing and connected to each of the NC pins which are divided into two groups. The exclusive DC channels are used to determine whether or not the NC pins form an electrical short circuit each other by connecting one NC pin to a ground level and while connecting the other NC pin to the power source having the DC measurement function.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: June 17, 1997
    Assignee: Advantest Corporation
    Inventor: Kazuhiko Sato
  • Patent number: 5640101
    Abstract: A probe system tests the electrical characteristics of chips arranged in a matrix on a semiconductor wafer. An XYZ stage movable in the directions of three-dimensional axes is disposed under a probe card having probes to be brought into contact with the electrode pads of the chips. A wafer table rotatable within a horizontal plane is disposed on the XYZ stage. A first image pickup means for picking up the probe images is mounted on the XYZ stage. A second image pickup means for picking up a wafer image is disposed above the table. The second image pickup means is movable horizontally to and from a use position under the probe card. A target is supported and moved by a driving member mounted on the XYZ stage, for aligning the focal points and optical axes of the first and second image pickup means. The target is moved between forward and retreat positions within and outside the field of view of the first image pickup means.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: June 17, 1997
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Motohiro Kuji, Haruhiko Yoshioka, Shinji Akaike, Shigeaki Takahashi
  • Patent number: 5640085
    Abstract: A temperature compensation circuit for a power measurement device includes an input sensor, with a temperature-dependent transmission factor (K.sub.H,T), connected to a signal processor with a temperature-dependent transmission factor (K.sub.S,T). Transmission factor (K.sub.S,T) of the signal processor is inversely proportional to a temperature-dependent reference voltage (U.sub.R,N,T), which is inputted to the signal processor in order to render the combined transmission factor (K.sub.H,T .multidot.K.sub.S,T) temperature independent. To accomplish this, a temperature coefficient value of reference voltage (U.sub.R,N,T) must be equal to the sum of a temperature coefficient value of transmission factor (K.sub.H,T) and a temperature coefficient value of transmission factor (K.sub.S,T). The desired temperature coefficient value of reference voltage (U.sub.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: June 17, 1997
    Assignee: Landis & Gyr Technology Innovation AG
    Inventors: Jan Petr, Erich Jeker
  • Patent number: 5640103
    Abstract: A method for detecting a departure from normal operation of an electric motor comprises obtaining a set of normal current measurements for a motor being monitored; forming clusters of the normal current measurements; training a neural network auto-associator using the set of normal current measurements; making current measurements for the motor in operation; comparing the input and output of the auto-associator; and indicating abnormal operation whenever the current measurements deviate more than a predetermined amount from the normal current measurements. The method models a set of normal current measurements for the motor being monitored, and indicates a potential failure whenever measurements from the motor deviate significantly from a model. The model takes the form of an neural network auto-associator which is "trained"--using clusters of current measurements collected while the motor is known to be in a normal operating condition--to reproduce the inputs on the output.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: June 17, 1997
    Assignee: Siemens Corporate Research, Inc.
    Inventors: Thomas Petsche, Charles Garrett
  • Patent number: 5638005
    Abstract: A tester exercises a DUT with a repetitive signal pattern, supplying a trigger signal for each repetition. The waveform on a conductor of the DUT is to be acquired by repeatedly measuring voltage at each of a number of sample points following the trigger, using a charged-particle probe system having an integrator-filter loop for analyzing energy of secondary particles. Before measurement at a sample point, integrator is reset and the filter voltage needed to settle the loop for the sample point is set using a predictive scheme. When the measurement is made, the predicted filter voltage is summed with the integrator output voltage to produce the actual filter voltage. The integrator then measures the error between the predicted filter voltage and the actual filter voltage needed to settle the loop. The time needed to settle the loop is thereby minimized. Various predictive schemes can be used.
    Type: Grant
    Filed: June 8, 1995
    Date of Patent: June 10, 1997
    Assignee: Schlumberger Technologies Inc.
    Inventors: Suresh N. Rajan, Kenichi Kanai
  • Patent number: 5635850
    Abstract: Process information obtained by a process section is input to a host computer. The process information includes information about a film, information about etching, information about cleaning, information about heat treatment, and information about a test. Yield information obtained by a D/S section is also input to the host computer. The host computer classifies wafers or lots into a plurality of quality ranks on the basis of these pieces of information, and supplies process conditions determined on the basis of the quality ranks to a burn-in section and a test section. The burn-in section and the test section respectively execute screening tests on the basis of the process conditions.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: June 3, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsugi Ogura
  • Patent number: 5635832
    Abstract: An IC carrier for loading thereon and transporting a device under test is used in an IC handler. The IC carrier is capable of easily and reliably loading thereon and positioning in place a device under test even the device under test having a reduced pitch between lead pins thereof. A box-like housing open in the top is formed and the bottom wall thereof has two generally parallel contact holes in the form of elongated slots, these two contact holes being spaced from each other by a spacing corresponding to that between two arrays of lead pins of the device under test. Each of the contact holes has a length corresponding to that of the associated lead pin array and a width sufficient to receive the associated lead pin array. Carrier guides are formed one adjacent each of opposite longitudinal ends of each of the contact holes and extend upwardly to a predetermined height from the bottom floor of the housing.
    Type: Grant
    Filed: February 8, 1996
    Date of Patent: June 3, 1997
    Assignee: Advantest Corporation
    Inventors: Akihiko Ito, Yoshihito Kobayashi
  • Patent number: 5633582
    Abstract: A combined signal level meter and leakage detector having a built-in antenna for the leakage detector, and dual clock frequency control of the microcontroller along with bandwidth switching for greater sensitivity in leakage detection mode. A data logging function is also provided. Control circuitry is also provided for avoiding receiver spurs by combined switching of multiple local oscillator frequencies, including combinations of high-side and low-side injection and IF shifting.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: May 27, 1997
    Assignee: Trilithic, Inc.
    Inventors: Dennis L. Orndorff, Dennis W. Staley
  • Patent number: 5633596
    Abstract: Fixtureless automatic test equipment for testing a printed wiring board having electrically conductive elements. The automatic test equipment of the present invention includes an array of modular integrated switching circuit (MISC) devices and test instrumentation fore determining the functionality of a workpiece. Each MISC includes an array of semiconductor dies mounted on a PWB interconnector for kiss touch deployment on a workpiece. All the PWB interconnectors form a test mattress of probes for deployment against a bare workpiece. Each semiconductor die includes a matrix of switching cells of which each switching cell terminates in a terminal. The PWB interconnector of each MISC connects the switching cell terminals to probes forming part of the test mattress.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: May 27, 1997
    Assignee: Key Solutions Ltd.
    Inventor: Avner Ilani
  • Patent number: 5631555
    Abstract: An apparatus of this invention emits light onto an EO probe and detects the light reflected by the EO probe by using an MSM photodetector. The MSM photodetector is applied with a voltage of a frequency nf.sub.0 +.DELTA.f.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: May 20, 1997
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hironori Takahashi, Musubu Koishi, Akira Takeshima
  • Patent number: 5631571
    Abstract: A system for functionally testing opto-electronic devices, such as fiber-optic infrared receiver photodiodes, in the integral wafer or other optical port-exposed status. The testing arrangement uses a portable optical probe for communicating optical signals between the testing apparatus and the tested device in coincidence with electrical energization and functional operation of the electro-optical device by the test apparatus. The optical probe signals may be correlated in time relationship or other manner with the electrical signals applied-to the device-under-test. The invention provides simple conversion between a conventional electrical semiconductor device probe station and an electro-optical device probe station.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: May 20, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Stephen Spaziani, Kenneth Vaccaro, William Waters
  • Patent number: 5631554
    Abstract: An integral electronic meter system diagnostics package including a microprocessor, storage memory, pre-select series of system diagnostic tests, and recording any results which exceed predefined programmable thresholds, and display means for displaying error and/or diagnostic messages identifying selected diagnostic data and/or errors discovered in the meter tests during a predefined period. The system automatically senses the type of electrical service in which the meter is installed.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: May 20, 1997
    Assignee: Schlumberger Industries, Inc.
    Inventors: Forrest W. Briese, Christophe J. A. Fouquet, Coy S. Lowe, Charles C. Hyder, John M. Schlarb