Abstract: A sequential connecting apparatus is used with an automatic testing apparatus to enable a plurality of electronic devices for testing to be automatically connected to the testing apparatus selectively in succession, thereby enabling unattended testing of the plurality of devices.

Abstract: An apparatus is disclosed for quickly testing individual wiring nets in a multi-layer device carrier. A central processing unit (CPU) controls a probe to sequentially engage contact pads on the carrier, each of which is electrically connected to a respective wiring net. The probe connects each wiring net to a network sensitive pulse generator circuit which generates a train of output pulses having a frequency dependent upon the transient behavior of the net under test. The stimulation of the net and the sensing of the net's response operate responsively to a feedback signal, which is also a signature signal. By connecting the net under test to the novel circuit, the combination of the novel circuit and the net under test generates the series of output pulses. The number of pulses generated in a predetermined period of time forms the signature of the net under test. A preferred embodiment is described which uses differential amplifiers to stimulate the net and to sense the net's response.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, it is possible to establish interconnection between the single dice or separate and package the dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: A process for inspecting an electrode plate having plural electrodes. The process includes the first step of using a rough alignment between the plate to be inspected and the standard inspecting plate so that the two lie on top of each other. One of the plates is then rotated relative to the other by a predetermined small angle. The electrical connection state between the two plates is then determined. A mathematical analysis of the position deviation between the two plates takes place. The analysis is based on the relative positions of the electrode inspected and the corresponding inspecting electrode before and after the rotation.

Abstract: Test jig apparatus for testing an integrated circuit chip that suppresses build-up and subsequent discharge of electrical charge on the test jig apparatus or on the chip. The test jig apparatus includes a base of selected material having a top surface of the same general shape and dimensions as the chip to be tested. Preferably, the entire top surface of the base is electrically grounded. The base has two or more side surfaces with side surface planes that are approximately perpendicular to a plane defining the top surface of the base. Each side surface accepts a side plate, made of a selected material such as ULTIM, that can be attached to or removed from the base. The side plate material resists electrical charge buildup and subsequent discharge so that the chip being tested is not subjected to electrical discharge from this source. In another embodiment, the side plates are replaced by plates mounted on the top surface of the base.

Abstract: The present invention relates to a probe needle wherein a conductive film is formed over a first insulating film formed around the outer periphery of a rod-like member through which a signal current flows, a second insulating film is formed over the outer periphery of the conductive film, and the conductive film is grounded. Since the rod-like member through which a signal current flows is thereby shielded, it is not affected by noise, and mutual crosstalk between signal currents is also prevented. Moreover, since ill effects caused by mutual contact with other probe needles is prevented by the second insulating film, reliable and stable measurement is possible.

Abstract: An electronic test instrument adapted for displaying only meaningful information notwithstanding the intermittent arrival of valid input signals due to probing operations is provided. Two independent measurement processes measure the input signal simultaneously. The first measurement process operates in a similar fashion to a digital storage oscilloscope (DSO) by successively sampling the input signal to produce waveform information which are selectively sent to an LCD display device which graphically displays the waveform. The second measurement process continually performs a stability assessment of the input signal by collecting a series of stability measurements of a selected input signal parameter, creating a moving average of the series, and comparing each new stability measurement to the moving average relative to stability criteria.

Abstract: A testing apparatus for testing and handling a multiplicity of devices, in particular electronic components such as integrated circuits or boards, comprises a test executor with a multiplicity of hierarchical operating levels assigned to respective physical or logical entities. At each level except the lowest one, test level controllers are provided which include a pre-activity sequence of tasks, a call to a lower operating level, a return from said lower operating level, and a post-activity sequence of tasks. At the lowest level, device test processors execute the actual test.

Abstract: A supplemental monitoring device which issues an error signal when the monitoring device loses motor drive pulses is disclosed. Also disclosed is providing a manufacturing system with a normally closed relay which controls the flag, thus advantageously providing a semiconductor system which automatically interrupts the ion beam in the event of a system malfunction.

Abstract: A network sensitive pulse generator circuit and a method of using the circuit to quickly detect faults in a net under test are described. The novel circuit generates pulses which depend upon the transient behavior of the net under test. The stimulation of the net and the sensing of the net's response operate responsively to a feedback signal, which is also a signature signal. By connecting the net under test to the novel circuit, the combination of the novel circuit and the net under test generates a series of output pulses. The number of pulses generated in a predetermined period of time forms the signature of the net under test. A preferred embodiment is described which uses differential amplifiers to stimulate the net and to sense the net's response. The differential amplifier which senses the net's response is connected to a circuit which produces the feedback/signature signal. The feedback/signal is then provide to the differential amplifiers to adjust their behavior.

Abstract: Automatic test equipment including a circuit to measure average current consumed by a device under test. The circuit operates during the execution of a test pattern which is not dedicated to measuring average current. The average current measuring circuit sets the measurement interval to account for a lag between the current drawn by the device under test and the current being measured.

Abstract: A method of inspecting cells of liquid crystal displays comprising the first step in which the empty TFTs in the active color LCD arrays are energized to charge the auxiliary pixel capacitor corresponding to the individual electrodes, the charged condition is maintained by deenergizing the TFT's, the electric charge is released through the source and drain of the TFTs and the resistor connected to the ground side thereof by re-energizing the TFTs, and the amount of the discharge is measured and the second step in which the same energizing, deenergizing, re-energizing, charging, discharging and measurement as done in the first step are made on the TFTs filled with a liquid crystal in the active color LCD arrays, the difference between the amounts of discharge measured in the first and second steps is integrated or the time constant of the amount of discharge measured in the first step is deducted from the time constant of the amount of discharge measured in the second step.

Abstract: A wafer prober comprises a wafer chuck for chucking a wafer and a probe card holding section for holding two or more probe cards. The wafer prober further comprises a test section for simultaneously testing a plurality of chips among chips in one wafer, with use of the two or more probe cards, while respectively making probe sections included in the two or more probe cards be in contact with external terminal sections of the plurality of chips.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: Quantitative dopant profile measurements are performed on a nanometer scale by using a scanning capacitance microsope. A nanometer scale tip of the microscope is positioned at a semiconductor surface, and local capacitance change is measured as a function of sample bias. The method incorporates a feedback system and procedure in which the magnitude of the AC bias voltage applied to the sample is adjusted to maintain a constant capacitance change as the tip is scanned across the sample surface. A one dimensional model is used to extract dopant density profiles from the measurements made by the scanning capacitance microscope.

Abstract: A testing contactor is provided for testing small-size semiconductor devices with large currents at high frequencies. Each semiconductor device to be tested has a plurality of leads. The testing contactor includes a plurality of first electric contact elements. A first Kelvin contact for a lead is formed of a first electric contact element in contact with the lead. The testing contactor further includes a plurality of second electric contact elements and a plurality of electric connection elements. An electric connection element in contact with the lead effectively extends the lead. A second Kelvin contact is formed of a second electric contact element and an electric connection element, the second electric contact element in contact with the electric connection element and the electric connection element in contact with the lead.

Abstract: A semiconductor integrated circuit fault analyzing apparatus includes an electron beam tester and controller. The electron beam tester includes an electron gun assembly for generating a primary electron beam and forms a voltage contrast image on the basis of a detection amount of secondary electrons obtained by irradiating the primary electron beam from the electron gun assembly onto a semiconductor integrated circuit serving as a target to be tested and supplied with a test pattern signal, thereby specifying a faulty circuit portion of the semiconductor integrated circuit using the formed voltage contrast image.

Abstract: A motor current analysis method and apparatus for monitoring electrical-motor-driven devices. The method and apparatus utilize high frequency portions of the motor current spectra to evaluate the condition of the electric motor and the device driven by the electric motor. The motor current signal produced as a result of an electric motor is monitored and the low frequency components of the signal are removed by a high-pass filter. The signal is then analyzed to determine the condition of the electrical motor and the driven device.

Abstract: A structure and method for achieving burn-in and full functional testing of a semiconductor wire bond die are provided. The structure comprises an electrical conductor which connects a wire bond pad to a solderable test contact laterally displaced from the wire bond pad. The solderable test contact is configured to facilitate electrical connection of an external testing device thereto for electrical testing and/or burn-in of integrated circuitry associated with the die, without direct physical contact to the wire bond pads. The structure does not need to be removed following the burn-in or test.

Abstract: An integrated circuit (IC) includes circuitry for generating a clock signal during both a normal mode of operation and a test mode of operation. During the normal mode, an input clock signal is delayed via a skew corrector. In test mode, an input test clock signal bypasses the skew corrector via a clock signal source selector. The clock signal source selector is controlled automatically by a mode detector that responds to the input clock signals to determine the mode of operation of the IC.