Patents Examined by Barry C. Bowser
  • Patent number: 5514978
    Abstract: Motor current and voltage waveforms are measured and converted to digitized current and voltage waveforms. A weighted discrete fourier transform is applied to the digitized current and voltage waveforms to obtain negative sequence current and voltage phasors; and the negative sequence current and voltage phasors are used to determine the existence of a turn fault. The use of the negative sequence current and voltage phasors can be performed by employing one of several techniques. In a first embodiment, an apparent negative sequence impedance is estimated by dividing the negative sequence voltage phasor by the negative sequence current phasor for comparison with a threshold negative sequence impedance. In a second, related embodiment, a current differential is estimated by dividing the negative sequence voltage phasor by a characteristic negative sequence impedance and subtracting the result from the negative sequence current phasor for comparison with a threshold current differential.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: May 7, 1996
    Assignee: General Electric Company
    Inventors: Rudolph A. A. Koegl, William J. Premerlani, Gerald B. Kliman
  • Patent number: 5514974
    Abstract: Method and test structures for accurately flagging metal failure on a semiconductor wafer include a monitor structure and a control structure, each of which has a plurality of metal segments. At least one metal segment of the monitor structure has a length prone to failure, while the length of the metal segments in the control structure are such that the control structure is resistant to metal failure. The monitor and control structures are predesigned to have equal resistance when there is no metal failure and a measurable resistance difference upon metal failure in that segment of the monitor structure prone to failure. Upon detecting metal failure in the test device, the wafer is flagged as potentially having metal failure in active circuitry interconnect wiring.
    Type: Grant
    Filed: October 12, 1994
    Date of Patent: May 7, 1996
    Assignee: International Business Machines Corporation
    Inventor: Dennis P. Bouldin
  • Patent number: 5514977
    Abstract: A pulse detection and conditioning circuit senses and conditions commutation pulses produced by a DC permanent magnet motor to determine motor position. The pulses are sensed using a resistor coupled in series with the motor, so that motor current and the included pulses are continuously sensed, even during motor braking. The serially coupled resistor also provides for sensing and conditioning of pulses of both polarities produced by bi-directional operation of the motor. The pulse detecting and conditioning is performed by circuitry which performs amplitude qualification as well as frequency filtering to effectively detect valid commutation pulses to the exclusion of noise and other unwanted signals. Capacitors coupled to the motor and internal capacitors provide the frequency filtering, while the amplitude qualification is provided by a balanced differential gain stage coupled through an adjustable differential gain stage with adjustable gain to a unity gain comparator.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: May 7, 1996
    Assignee: Linfinity Microelectronics, Inc.
    Inventor: Dan Agiman
  • Patent number: 5512840
    Abstract: The subject clips are adapted from commercially available screw setters. Shortening of the setters and attachment of electrical conductors converts the setters to electrical test clips.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: April 30, 1996
    Inventor: Paul V. Nogaki
  • Patent number: 5510722
    Abstract: A test fixture for testing printed circuit boards on a test computer includes a base, a probe plate on the base and a top plate in spaced relation above the probe plate. The probe plate has a predetermined array of spring loaded primary contact probes mounted therein, and the top plate has a plurality of secondary contact probes mounted therein in alignment with and in the same predetermined array as the primary contact probes in the probe plate. The top plate is adapted for receiving and positioning a printed circuit board thereon so that predetermined areas of the printed circuit board are aligned with the secondary contact probes, and the fixture is actuatable for drawing the top plate toward the probe plate to cause the primary contacts to engage the secondary contacts and to thereby move the secondary contacts into engagement with the predetermined areas of the printed circuit board.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: April 23, 1996
    Assignee: TTI Testron, Inc.
    Inventor: Bruce A. Seavey
  • Patent number: 5510723
    Abstract: An apparatus for testing an unencapsulated, diced semiconductor device comprises a test head. The test head comprises a carousel table having a chamfered portion and a chamfered pedestal. While testing is pending the pedestal rests against the chamfered portion of the carousel table, and the pedestal receives a semiconductor device to be tested. The carousel table rotates 90.degree. to position the semiconductor device under the test head. The pedestal is lifted, and the chamfered nature of the pedestal and the carousel table allow for adjustments to the pedestal in the X-, Y-, and theta-directions to align the die with a probe responsive to signals from a camera positioned above the probe. Once the die is aligned, the pedestal continues to rise until contact is made between bond pads on the die and the probe, and testing is performed.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: April 23, 1996
    Assignee: Micron Custom Manufacturing, Inc. USA
    Inventors: Robert L. Canella, Warren M. Farnworth
  • Patent number: 5508617
    Abstract: The current invention is directed to a method of measuring an electric power and in particular to a precise power measurement by measuring a current and a voltage of high-frequency distortion waves. The current power measuring method is based upon a summation of the power values measured for every frequency component of the distortion wave. After being frequency converted in a mixer 5, a voltage is inputted from an input terminal 1 through a voltage amplifier 3 to a vector voltmeter 7. A current is supplied into an input terminal 2, and converted into a voltage signal by a current-to-voltage converter 4. Then, the voltage signal is frequency-converted in a mixer 6, and thereafter inputted into a vector voltmeter 8. The input signals to the mixers 5 and 6 are separated into frequency components by sweeping of a local signal generator 10, which are measured by the vector voltmeters.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: April 16, 1996
    Assignee: Hewlett-Packard Company
    Inventor: Yasuaki Komatsu
  • Patent number: 5508628
    Abstract: A pivoting beam or lever is used to open and close burn-in and test sockets which employ laterally moving cammed plates to form electrical contact between electrical contact fingers within the socket and terminals depending from an electronic device package. The pivoting beam is oriented and adapted for operation by vertically applied forces so that opening and closing the socket is easily automatible using the pick and place equipment conventionally used to insert and remove electronic device packages from open top sockets.
    Type: Grant
    Filed: February 1, 1995
    Date of Patent: April 16, 1996
    Inventor: Wayne K. Pfaff
  • Patent number: 5506514
    Abstract: A method and apparatus for electrically interconnecting various electronic elements, including circuit components, assemblies, and subassemblies. A particle enhanced material metal contact layer, having a surface, formed on the electronic elements, includes particles of greater hardness disposed on and/or within the metal contact layer, which particles form protuberances that concentrate stress when said contact surface is brought into contact with an opposing surface under pressure, to thereby penetrate the opposing surface and form a metal matrix between the two surfaces.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: April 9, 1996
    Assignee: Particle Interconnect, Inc.
    Inventor: Louis Difrancesco
  • Patent number: 5506513
    Abstract: A microwave test fixture (10) for testing a two port microwave integrated circuit (MIC) (11) including a first signal block (12) and an opposing second signal block (14). Each signal block (12 and 14) includes an inside face (20 and 36) with an overhang portion (30 and 46), a vertical channel (52 and 62) and a connector aperture (70 and 72). The connector apertures (70 and 72) each receive a connector assembly (78 and 80) that includes a coaxial connector (82 and 108), a conductive sleeve (84 and 110) and an insulative bead (112 and 86). A signal contact (88 and 114) extends from an inner conductor 90 of each coaxial connector (82 and 108), through the insulative bead (112 and 86) and vertical channel (52 and 62) and out from the inside face (20 and 36) below the overhang portion (30 and 46). Each signal contact (88 and 114) includes a contact spring section (100).
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: April 9, 1996
    Inventor: Helmut Bacher
  • Patent number: 5506516
    Abstract: In a method of inspecting an active matrix substrate of the invention, the active matrix substrate includes a pixel portion having a plurality of pixels arranged in a matrix, a plurality of scanning lines and data lines for driving the pixel portion, and a drive circuit having one and more video lines, one end of each of the plurality of data lines being connected to one of the video lines. The method of the invention includes the steps of: providing one or more inspecting lines, the other end of each of the plurality of data lines being connected to one of the inspecting lines; applying an inspecting signal to each of the inspecting lines, with the drive circuit being in operation; and inspecting the drive circuit and the plurality of data lines, based on at least one of the signals output from the or each of the video lines in accordance with the inspecting signals.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: April 9, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Yasuhiro Matsushima, Takayuki Shimada, Yutaka Takafuji
  • Patent number: 5506499
    Abstract: Each touchdown of a probe card during wafer-sort testing of integrated circuits can leave a gouge in the pad metal. These gouges reduce the reliability of any wire bond to that pad as voids can be left in the bond where the gouges are. A second auxiliary test pad is adjacent to the primary bonding pad. This second auxiliary test pad is electrically connected to the primary bonding pad. Thus probes can land on the second auxiliary pad rather than the primary pad. Gouges are made on the second pad rather than the primary pad. This second test pad allows for multiple probing. Multiple probing is needed for testing large embedded memories on large logic chips such as video controllers. The yield of large memories is increased by laser repair. Probing and testing is required both before and after laser repair using a memory test machine. However, a logic test machine is used to test the logic controller portion of the IC, but cannot generate the millions of test vectors needed to fully test the embedded memory.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: April 9, 1996
    Assignee: NeoMagic Corp.
    Inventor: Deepraj S. Puar
  • Patent number: 5504435
    Abstract: A testing contactor is provided for testing small-size semiconductor devices with large currents at high frequencies. Each semiconductor device to be tested has a plurality of leads. The testing contactor includes a plurality of first electric contact elements. A first Kelvin contact for a lead is formed of a first electric contact element in contact with the lead. The testing contactor further includes a plurality of second electric contact elements and a plurality of electric connection elements. An electric connection element in contact with the lead effectively extends the lead. A second Kelvin contact is formed of a second electric contact element and an electric connection element, the second electric contact element in contact with the electric connection element and the electric connection element in contact with the lead.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: April 2, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Romano Perego
  • Patent number: 5504437
    Abstract: A stage 130 includes a metal base and an anti-metal contamination film formed on the metal base a semi-conductor wafer 120. The anti-metal contamination film is constructed of a material selected from the group consisting of a semi-conductor film, a semi-conductor oxide film, a semi-conductor nitride film, a semi-conductor carbide film, and a polytetrafluoroethylene film. The rear face of the semi-conductor wafer 120 mounted on the stage 130 is in direct contact with the anti-metal contamination film but not with the metal surface. The anti-metal contamination film, which does not contain simple substances of metals, effectively protects the rear face of the semi-conductor wafer 120 from contamination metal.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: April 2, 1996
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Sadao Hirae, Hiroshi Okada, Hideaki Matsubara
  • Patent number: 5498970
    Abstract: A test socket for temporary connection of a ball grid array integrated circuit device to a test circuit includes an array of contacts each including two cantilever arms biased toward each other and terminating in tips adapted to capture one ball of the device.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: March 12, 1996
    Assignee: Minnesota Mining and Manufacturing
    Inventor: Kurt H. Petersen
  • Patent number: 5498957
    Abstract: An appliance for the coulometric measurement of the thickness of metallic coatings comprises a measuring probe (11) and a reversing pump device (12) with the aid of which the electrolyte fluid can be conveyed from a reservoir chamber (19) of the measuring probe (11) into the measuring chamber (17) thereof and back again. The measuring probe (11), together with the reversing pump device (12), forms a functional unit which, as a whole, can be coupled to the support device (13) and be uncoupled therefrom again. In the process, the pump drive (14) remains on the support device (13). A change of measuring probes, charged so as to be ready for service, is thus possible simply and quickly, which permits rapid measurement of a plurality of successive coatings on one measurement object to be performed. The functional unit of measuring probe and reversing pump device prevents unintentional outflow of the electrolyte fluid.
    Type: Grant
    Filed: November 3, 1994
    Date of Patent: March 12, 1996
    Inventor: Helmut Fischer
  • Patent number: 5497103
    Abstract: A test apparatus and method for testing circuitized substrates such as printed circuit boards or ceramic substrates having one or more chips thereon. The apparatus includes one substrate (e.g., printed circuit board) located on a base and adapted for having another circuitized substrate (e.g., flexible circuit) positioned thereon and electrically coupled to conductive elements (e.g., copper pads) thereof. Elastomeric members may be used to force the flexible circuit against the conductors of the substrate being tested, this substrate positioned either within or upon a cover which is located over the flexible circuit and which assists in compressing the flexible circuit against the printed circuit board's conductive elements to assure positive connection therewith. The cover may also include elastomeric members to facilitate such connection and a pivotal arm for being actuated to engage the substrate being tested.
    Type: Grant
    Filed: January 25, 1995
    Date of Patent: March 5, 1996
    Assignee: International Business Machines Corporation
    Inventors: William S. Ebert, David E. Engle, Kishor V. Desai, Thomas G. Macek
  • Patent number: 5495180
    Abstract: A small sized energy conveying and signal dissipating loading apparatus for use in the testing of a transistor of the high gain high frequency type is disclosed. The energy conveying and loading device of the invention employs a transmission line-like network of distributed components in order to roll off and dampen or dissipate the high frequency alternating current response of the transistor under test while also being electrically invisible for measuring the low frequency or DC characteristics of the transistor under test. The described energy communicating and loading apparatus is compatible with the temperatures of a test environment for even the most extreme environment transistor devices and allows convenient placement in the test environment immediately adjacent the transistor under test. The load allows testing of multiple transistor devices with reasonable space and cost requirements.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: February 27, 1996
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Chern I. Huang, Mark Calcatera
  • Patent number: 5493210
    Abstract: A combined signal level meter and leakage detector having a built-in antenna for the leakage detector, and dual clock frequency control of the microcontroller along with bandwidth switching for greater sensitivity in leakage detection mode. A data logging function is also provided. Control circuitry is also provided for avoiding receiver spurs by combined switching of multiple local oscillator frequencies, including combinations of high-side and low-side injection and IF shifting.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: February 20, 1996
    Assignee: Trilithic, Inc.
    Inventors: Dennis L. Orndorff, Dennis W. Staley
  • Patent number: 5493238
    Abstract: In a device parameter extracting apparatus, a set of drain currents I.sub.D (i,j) is measured from each of a plurality of MISFET devices of different gate lengths L(i) by successively applying gate voltages V.sub.G (i,j) to each of the MISFET devices for a predetermined drain voltage, where i identifies each of the MISFET devices and j is an integer. A set of drain currents I.sub.D (i,k) is interpolated from the measured drain currents I.sub.D (i,j) such that the interpolated drain currents correspond respectively to predetermined ones of voltage differences V.sub.G (i,j)-V.sub.TH (i), where k is an integer and V.sub.TH (i) is a threshold voltage of each of the MISFET devices. A set of regression lines R(k)=a(k)L(i)+b(k) is derived in a coordinate space from a set of relationships between V(k)/I.sub.D (i,k) and the gate lengths L(i) of the devices, where a(k) and b(k) are constants, where V(k) represents the predetermined ones of voltage differences.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: February 20, 1996
    Assignee: NEC Corporation
    Inventor: Kiyoshi Takeuchi