Patents Examined by Benjamin L. Utech
  • Patent number: 6503565
    Abstract: A metal surface which has been cleaned using an alkaline based solution is treated with an acidic solution which contains rear earth ions to remove any smut which may have been produced during the alkaline cleaning. A coating is formed on the cleaned surface using a different acidic solution containing rare earth cations which have multiple valence states. When the surface is reacted with coating solution, an increase in the pH at the metal surface indirectly results in precipitation of a rare earth metal such as cerium onto the surface. Alternatively, after the removal of the smut, the surface may be coated using a painting technique.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: January 7, 2003
    Assignee: Commonwealth Scientific and Industrial Research Organisation
    Inventors: Anthony Ewart Hughes, Karen Joy Hammon Nelson, Russell James Taylor, Bruce Roy William Hinton, Mark Julian Henderson, Lance Wilson, Sally Ann Nugent
  • Patent number: 6503322
    Abstract: An electrical resistance heater for use in a crystal puller used for growing monocrystalline silicon ingots according to the Czochralski method comprises a heating element sized and shaped for placement in a housing of the crystal puller generally above a crucible in spaced relationship with the outer surface of the growing ingot for radiating heat to the ingot as it is pulled upward in the housing relative to the molten silicon. The heating element has an upper end and a lower end. The lower end of the heating element is disposed substantially closer to the molten silicon than the upper end when the heating element is placed in the housing. The heating element is constructed such that the heating power output generated by the heating element gradually increases from the lower end to the upper end of the heating element.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: January 7, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Richard G. Schrenker, William L. Luter
  • Patent number: 6500255
    Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: December 31, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Paolo Mutti
  • Patent number: 6500763
    Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: December 31, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-won Kim, Sang-don Nam, Wan-don Kim, Kab-jin Nam
  • Patent number: 6500350
    Abstract: A method is provided for forming a patterned layer of resistive material in electrical contact with a layer of electrically conducting material. A three-layer structure is formed which comprises a metal conductive layer, an intermediate layer formed of material which is degradable by a chemical etchant, and a layer of resistive material of sufficient porosity such that the chemical etchant for said intermediate layer may seep through the resistive material and chemically degrade said intermediate layer so that the resistive material may be ablated from said conductive layer wherever the intermediate layer is chemically degraded. A patterned photoresist layer is formed on the resistive material layer. The resistive material layer is exposed to the chemical etchant for said intermediate layer so that the etchant seeps through the porous resistive material layer and degrades the intermediate layer. Then, portions of the resistive material layer are ablated away wherever the intermediate layer has been degraded.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: December 31, 2002
    Assignee: Morton International, Inc.
    Inventors: Andrew T. Hunt, Wen-Yi Lin, Shara S. Shoup, Richard W. Carpenter, Stephen E. Bottomley, Tzyy Jiuan Hwang, Michelle Hendrick
  • Patent number: 6497783
    Abstract: A plasma processing apparatus is disclosed which comprises a container which can be evacuated; a gas supply means for supplying a gas to the inside of the container; and a microwave supply means for supplying microwaves to generate a plasma in the container, the plasma being utilized to process an article, wherein the microwave supply means is a microwave applicator which is provided with an annular waveguide having a planar H-plane with a plurality of slots provided apart from each other and a rectangular cross section perpendicular to the traveling direction of microwaves and which supplies microwaves to the inside of the container through a dielectric window of the container from the plurality of slots provided in the planar H-plane, and wherein the gas supply means is provided a gas emission port through which the gas is emitted toward the planar H-plane.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: December 24, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobumasa Suzuki, Manabu Matsuo, Hirohisa Oda
  • Patent number: 6498110
    Abstract: A method of removing ruthenium silicide from a substrate surface which comprises exposing the ruthenium silicide surface to a solution containing chlorine and fluorine containing chemicals. In particular, said solution is designed to react with said ruthenium silicide film such that water-soluble reaction products are formed.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: December 24, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brenda D. Kraus, Michael T. Andreas
  • Patent number: 6498106
    Abstract: An undesirable side effect of some processes that are used for forming dual gate devices is the formation of defects at the interface between the two oxide layers of different thickness. This problem has been solved by preceding the HF wet dip (that is used to thin out a selected area of oxide) with exposure of the photoresist to a low power plasma that includes some oxygen. This treatment removes unsaturated chemical bonds from the resist surface and prevents the formation of SiC based defects. Such defects could cause polysilicon lines to short or open, depending on their size.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: December 24, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Pin-Yi Hsin, Yu-Lun Lin, Jyh-Shiou Hsu
  • Patent number: 6498103
    Abstract: A method for manufacturing a solid-state imaging device includes forming a transfer channel portion and a light-receiving portion in a silicon substrate; forming a silicon oxide film on the silicon substrate; forming a silicon nitride film on the silicon oxide film, the silicon nitride film acting as a gate insulating film together with the silicon oxide film above the transfer channel portion and acting as an anti-reflection film above the light-receiving portion; forming a protection film on the silicon nitride film; forming a polysilicon film above the silicon nitride film via the protection film at least above the light-receiving portion; and etching the polysilicon film so as to form a transfer electrode above the transfer channel portion. The etching of the polysilicon film is carried out so that the polysilicon film is removed above the light-receiving portion while the protection portion remains.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: December 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Rieko Nishio, Takumi Yamaguchi, Toshihiro Kuriyama, Hiroyuki Senda
  • Patent number: 6495464
    Abstract: A method of creating and using a polishing substrate having a coating layer that includes providing a substrate having a predetermined pattern disposed on a surface of the substrate and coating the surface of the substrate with an abrasive to form a coated substrate conforming to the predetermined pattern is described. In addition, an apparatus enabling preparation and use of a fixed abrasive polishing member is described that includes a patterned substrate, an abrasive coating a surface of the patterned substrate and a vacuum deposition chamber in which the abrasive is applied to the surface of the substrate. In addition, rather than a fixed abrasive, non-abrasive material may be applied to the surface of the patterned substrate, in which case, a conventional slurry may be used in planarization of an applied semiconductor wafer.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: December 17, 2002
    Assignee: LAM Research Corporation
    Inventors: John M. Boyd, Michael S. Lacy
  • Patent number: 6494984
    Abstract: A machine for processing the front side of a flat media workpiece, such as a silicon wafer, seals the backside of the wafer from processing chemicals. A rotor has an inside ring and an outside ring protruding from the rotor face. The inside ring and outside ring are separated by an annular groove in the rotor. A O-ring is positioned between the inside ring and the outside ring. A membrane extends from the inside ring, over the annular groove and the O-ring, to the outside ring. The membrane and face of the rotor form a sealable wafer back face chamber between them. Vacuum is applied to the back face chamber to hold the wafer against the membrane. The back surface of the wafer is sealed from processing chemicals, which are allowed to contact only the front surface and edges of the wafer.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: December 17, 2002
    Assignee: Semitool, Inc.
    Inventor: Steven L. Peace
  • Patent number: 6494162
    Abstract: A method for manufacturing a semiconductor device including preparing a multi-chamber system having at least first and second chambers, the first chamber for forming a film and the second chamber for processing an object with a laser light; processing a substrate in one of the first and second chambers; transferring the substrate to the other one of the first and second chambers; and processing the substrate in the other one of the chambers, wherein the first and second chambers can be isolated from one another by using a gate valve.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: December 17, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 6495462
    Abstract: A microelectronic component is made by providing a starting structure having a dielectric layer and leads on a surface of the dielectric layer. Ends of the leads are connected to contacts on a microelectronic element, such as the contacts on a semiconductor chip or wafer. The dielectric layer is then etched to partially detach the leads from the dielectric layer, leaving at least one end of each lead permanently connected to the dielectric layer. The remainder of the lead may be fully or partially detached from the dielectric layer. If the remainder of the lead is only partially detached, the connecting elements that connects the leads to the polymeric layer can be broken or peeled away from the leads during the step of moving the microelectronic element and dielectric layer away from one another.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: December 17, 2002
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Hamid Eslampour, Konstantine Karavakis
  • Patent number: 6492277
    Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: December 10, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
  • Patent number: 6492279
    Abstract: A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0.3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: December 10, 2002
    Assignee: Micron Technology, Inc.
    Inventors: David S. Becker, Bradley J. Howard, Kevin G. Donohoe
  • Patent number: 6491833
    Abstract: This patent a method of manufacturing a Dual Chamber Single Vertical Actuator Ink Jet Printer print head wherein an array of nozzles are formed on a substrate utilising planar monolithic deposition, lithographic and etching processes. Preferably, multiple ink jet heads are formed simultaneously on a single planar substrate such as a silicon wafer. The print heads can be formed utilising standard vlsi/ulsi processing and can include integrated drive electronics formed on the same substrate. The drive electronics preferably being of a CMOS type. In the final construction, ink can be ejected from the substrate substantially normal to the substrate.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: December 10, 2002
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 6492274
    Abstract: Autoclaving slurries of porous, inorganic oxide particles results in an increased abrasiveness of the particles as reflected in increased removal rates of a polished substrate at standard polishing conditions in chemical mechanical polishing operations. Slurries having novel abrasion properties, especially for silica-based slurries, are created. The increase in particle abrasivity strongly correlates with a decrease in particle surface area as determined by N2 adsorption (BET method). As a result, methods for obtaining a desired abrasivity for a slurry can be practiced by heating a slurry of inorganic oxide particles to a BET surface area previously identified as associated with the abrasivity desired. The resulting slurries can be used in conventional polishing machinery. The method is particularly suitable for preparing silica-based abrasive slurries.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: December 10, 2002
    Assignee: W. R. Grace & Co.-Conn.
    Inventor: James Neil Pryor
  • Patent number: 6492186
    Abstract: A method for determining an endpoint for an oxygen free plasma stripping process for use in semiconductor wafer processing. The method comprises exciting a gas composition containing a nitrogen gas and a reactive gas to form the oxygen free plasma. The oxygen free plasma reacts with a substrate having a photoresist and/or residues thereon to produce emitted light signals corresponding to an oxygen free reaction product. The endpoint is determined by optically measuring a primary emission signal of the oxygen free reaction product at a wavelength of about 387 nm. The endpoint is determined when the plasma no longer reacts with the photoresist and/or residues on the substrate to produce the emitted light at about 387 nm, an indication that the photoresist and/or residues have been removed from the wafer. Secondary emission signals of the oxygen free reaction product at about 358 nm and 431 nm can also be monitored for determining the endpoint.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: December 10, 2002
    Assignee: Eaton Corporation
    Inventors: Qingyan Han, Palani Sakthivel, Ricky Ruffin, Andre Cardoso
  • Patent number: 6489245
    Abstract: A method for reducing erosion of a mask while etching a feature in a first layer underlying the mask is disclosed. The first layer is disposed on a substrate, with the substrate being positioned on a chuck within in a plasma processing chamber. The method includes flowing an etchant source gas into the plasma processing chamber and forming a plasma from the etchant source gas. The method further includes pulsing an RF power source at a predefined pulse frequency to provide pulsed RF power to the chuck. The pulsed RF power has a first frequency and alternates between a high power cycle and a low power cycle at the pulse frequency. The pulse frequency is selected to be sufficiently low to cause polymer to be deposited on the mask during the low power cycle.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: December 3, 2002
    Assignee: Lam Research Corporation
    Inventors: Jaroslaw W. Winniczek, Vahid Vahedi
  • Patent number: 6489246
    Abstract: A method of manufacturing an image sensor, the method comprises the steps providing a substrate having a gate insulating layer abutting a portion of the substrate; depositing a silicon layer on the gate insulating layer; creating a plurality of openings in the deposited silicon layer for forming a plurality of etched deposited silicon; growing an oxide on first surfaces of the etched deposited silicon which first surfaces initially form a boundary for the openings; coating photoresist in the plurality of openings between the first surfaces of the oxidized silicon; and exposing the photoresist for removing the photoresist which overlies the silicon and retains a portion of the photoresist in the openings and on the first surface of the oxidized silicon.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: December 3, 2002
    Assignee: Eastman Kodak Company
    Inventors: Joseph R. Summa, David L. Losee, Eric J. Knappenberger