Abstract: A giant magnetoresistance (GMR) sensor is formed using a self organizing diblock copolymer as an etching mask. The diblock copolymer is deposited over a magnetic layer and is self organized into regions of two discrete thicknesses; higher thickness island regions separated by lower thickness valley regions. After the diblock layer is self organized, an etching of process is performed to remove the polymer material from the valley regions as well as the underlying magnetic material. After etching, a patterned magnetic thin film of submicron islands of magnetic material, preferably having a diameter in the single domain range, remain under the mesa region. The islands are interconnected by a non-magnetic, conductive layer with electrical contacts coupled thereto to complete the GMR sensor. When the sensor is not subjected to a magnetic field, the magnetic alignment of the islands is random, and electron scattering results in a high resistance state.

Abstract: A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.

Abstract: A method for producing a silicon single crystal, the method being capable of suppressing the dislocation of a single crystal. When a silicon single crystal is produced by a Czochralski method in which a horizontal magnetic field or a cusp magnetic field is applied and the single crystal during growth is dislocated, the single crystal with dislocations is dissolved in a nonmagnetic field condition and thereafter a magnetic field is applied again to pull up the silicon single crystal. The flow rate of argon gas is designed to be 100 L/min or more and the pressure in a furnace is designed to be 6700 pa or less when the single crystal with dislocations is dissolved.

Abstract: A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks typically consist of the following layers: silicon nitride (310), tungsten (320), titanium nitride (330), and polysilicon (340). The process includes one step for each of the four layers in the gate stack, and one step to ash the photoresist. These five process steps can preferably be performed in four separate chambers on a cluster tool platform. The innovative etch process of the present invention fabricates gates with lengths of 0.25 microns and below with excellent profile, excellent linewidth uniformity across the wafer, and minimal loss of the gate oxide.

Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Abstract: A novel batch processing system used, for example, in plasma etching and chemical vapor deposition, wherein the pressure in the reactor is cycled through a varying pressure to increase the transfer of the reactant materials to the center of the wafer. One version of the invention provides a method that includes the steps of (I) feeding reactant gases into a reaction vessel, (ii) exhausting unused reactive gases and/or reaction by-products from the reaction vessel, and (iii) cycling the pressure in the reaction vessel between a higher pressure Phigh and a lower pressure Plow. Another version of the invention provides an apparatus that comprises (I) a reaction vessel, (ii) a feed means for feeding reactive gases into the reaction vessel, (iii) an exhaust means for exhausting unused reactive gases and/or reaction by-products from the reaction vessel, and (d) a pressure control means for cycling the pressure in the reaction vessel between a higher pressure Phigh and a lower pressure Plow.

Abstract: A contact structure for establishing electrical connection with contact targets. The contact structure is formed of a contactor carrier and a plurality of contactors. The contactor has an upper end oriented in a vertical direction, a straight beam portion oriented in a direction opposite to the upper end and having a lower end which functions as a contact point for electrical connection with a contact target, a return portion returned from the lower end and running in parallel with the straight beam portion to create a predetermined gap therebetween, a diagonal beam portion provided between the upper end and the straight beam portion to function as a spring.

Abstract: A method for wet etching a gallium nitride compound-based semiconductor is disclosed. The method uses an aqueous solution containing an oxidizing agent such as peroxydisulfate ions. The sample and solution are irradiated with visible or ultraviolet light in order to promote the etching.

Abstract: A method of manufacturing a ridge-shaped 3-dimensional waveguide, has the steps of: forming a crystal film made of a second ferroelectric oxide non-linear crystal having a refractive index higher than that of a substrate made of a first ferroelectric oxide non-linear crystal on the substrate; forming a metal film on the crystal film; forming a mask by etching the metal film; and forming a ridge portion by selectively removing the crystal film through the mask by a dry etching method.

Abstract: There is provided a method of forming an interlayer insulating film having a dual-damascene structure, a contact hole and a deep trench mask using an organic silicon film. The shape of polysilane or the like is processed so that polysilane is used as an interlayer insulating film having a dual-damascene structure to control the shape and depth and prevent borderless etching which must be solved when a trench is formed. Polysilane and an insulating film are formed into a laminated structure so as to be integrated with each other after a dry etching step has been completed to easily form a contact hole having a high aspect ratio. The surface of polysilane is selectively formed into an insulating film so as to be used as a mask for use in a dry etching step. Polysilane for use as an anti-reflective film or an etching mask is changed to an oxide film or a nitride film so that films are easily removed.

Abstract: A method of manufacturing a semiconductor device having features with a dimension of ½the minimum pitch wherein the minimum pitch is determined by the parameters of the manufacturing process being used to manufacture the semiconductor device. A target layer of material to be etched with dimensions of ½the minimum pitch is first etched with masks having a dimension of the minimum pitch and the target layer of material is then etched with the masks offset by ½the minimum pitch.

Abstract: A method of polishing a semiconductor substrate by adjusting the polishing composition with a BTA concentration that raises the metal removal rate when polishing at a relatively high polishing pressure, and that minimizes the metal removal rate when polishing metal in trough at a lower polishing pressure; and adjusting the polishing pressure on metal in each trough to a level that removes metal from trough at a minimized removal rate, while simultaneously polishing the excess metal with a higher polishing pressure.

Abstract: A substrate support comprises an electrode and a dielectric layer covering the electrode, the dielectric layer having a surface to receive a substrate. A gas feed-through provides a gas to the surface of the dielectric layer and comprises a conduit extending through one or more of the dielectric layer and electrode. A dielectric insert in the gas feed-through has a passage therein that allows the gas to be flowed therethrough. Two opposing electrically conducting cups are around the passage in the dielectric insert.

Abstract: A method for forming hybrid low-k film stack is disclosed, in which an organic spin-on low-k material and CVD low-k material are combined to avoid thermal stress effect. This invention also provides a method for applying hybrid low-k film stack to dual damascene process.

Abstract: A process forms a single crystal silicon ingot from varying sized pieces of polycrystalline silicon source material according to the Czochralski method. The process comprises placing into a crucible on the bottom a generally polygonal-shaped concentric array of rod-shaped polycrystalline silicon pieces having obliquely cut ends. The method of stacking the polycrystalline silicon pieces in the crucible allows for a denser packing of silicon in the crucible, can be accomplished in a quicker time then conventional packing methods, and has the potential for less damage to the crucible bottom, when comparing to standard packing methods using a size assortment of irregular shaped silicon pieces.

Abstract: A furnace for growing a high volume of crystals includes a plurality of individual growth stations and first and second heater matrixes. Each individual growth station has a crucible and an insulating container generally surrounding the crucible and thermally isolating the crucible from the other individual growth stations. The first and second heater matrices each include at least two legs electrically connected in parallel and each of the legs have at least two resistance heaters electrically connected in series. Each of the individual growth stations have at least one of the resistance heaters within the first heater matrix and at least one of the resistance heaters within the second heater matrix associated therewith. The resistance heaters of the first heater matrix are located above the crucibles and are preferably adapted to provide a homogeneous temperature across tops of the crucibles.

Abstract: A vacuum valve assembly for use in a vacuum processing chamber includes a seat defining an opening in the vacuum valve, with the seat having a sealing face adjacent the opening and normal to the direction of the opening; and a gate having a sealing face adapted to mate with the seat sealing face, the gate being movable toward and away from the seat sealing face to seal and open the vacuum valve opening. A continuous elastomeric seal extends around the vacuum valve opening between the gate sealing face and the seat sealing face of sufficient size such that when the gate is positioned to seal the vacuum valve opening, there exists a gap between the gate sealing face and the seat sealing face. A purge gas port system, disposed in the seat or in the gate, has an inlet for a purge gas, an essentially continuous outlet extending around the vacuum valve opening and adjacent the elastomeric seal and gap, and a manifold system connecting the inlet and the outlet.

Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.

Abstract: A developing processing apparatus for supplying a developing solution to a wafer on which a photoresist film has been formed to thereby perform developing processing includes a wafer holding portion for horizontally holding the wafer, a linear nozzle held above the wafer holding portion for supplying the developing solution onto the wafer while moving in a predetermined horizontal direction, and a resistance bar for imparting discharge resistance to the developing solution discharged from the linear nozzle. This allows all discharge ports to discharge the developing solution uniformly, especially even when discharge pressure for the developing solution to be supplied is low in development of a scan method using a linear nozzle or a slit nozzle.