Abstract: A method and apparatus for releasably attaching a planarizing medium, such as a polishing pad, to the platen of a chemical-mechanical planarization machine. In one embodiment, the apparatus can include several apertures in the upper surface of the platen that are coupled to a vacuum source. When a vacuum is drawn through the apertures in the platen, the polishing pad is drawn tightly against the platen and may therefore be less likely to wrinkle when a semiconductor substrate is engaged with the polishing pad during planarization. When the vacuum is released, the polishing pad can be easily separated from the platen. The apparatus can further include a liquid trap to separate liquid from the fluid drawn by the vacuum source through the apertures, and can also include a releasable stop to prevent the polishing pad from separating from the platen should the vacuum source be deactivated while the platen is in motion.

Abstract: In a method of fabricating a microstructure for microfluidics applications, a first layer of etchable material is formed on a suitable substrate. A mechanically stable support layer is formed over the etchable material. A mask is applied over the support to expose at least one opening in the mask. An anistropic etch is then performed through the opening to create a bore extending through the support layer to said layer of etchable material. After performing an isotropic etch through the bore to form a microchannel in the etchable material extending under the support layer, a further layer is deposited over the support layer until overhanging portions meet and thereby close the microchannel formed under the opening.

Abstract: In one aspect, the present invention provides sets of crystallization solutions that each comprise a crystallization solution set selected from the group of crystallization solution sets consisting of Crystallization Solution Set 1, Crystallization Solution Set 2, Crystallization Solution Set 3, Crystallization Solution Set 4 and Crystallization Solution Set 5. In another aspect, the present invention provides kits that each comprise at least one crystallization plate and a Crystallization Solution Set of the invention.

Abstract: A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an etchant mixture containing a fluorinated organic, oxygen and an inert gas and continuously increasing and/or decreasing the amount of oxygen in the etchant mixture during etching through the silicon oxide film.

Abstract: A method for forming a silicon island used for forming a TFT or thin film diode comprises the step of pattering a silicon film with a photoresist mask. In order to prevent the contamination of the semiconductor film due to the photoresist material, a protective film such as silicon oxide is interposed between the semiconductor film and the photoresist film. Also, the protective film is preferably formed by thermal annealing or light annealing in an oxidizing atmosphere.

Abstract: A substrate processing chamber 25 comprising a substrate support 85, and a wall 24 about the substrate support 85, the wall 24 having a radiation absorbing surface 36 adapted to preferentially absorb radiation having wavelengths in the visible or infra-red spectrum.

Abstract: A process for preparation of silicon carbide by depositing silicon carbide on at least a part of a surface of a substrate having on its surface undulations extending approximately in parallel with each other, wherein a center line average of said undulations is in a range of from 3 to 1,000 nm, gradients of inclined planes of said undulations are in a range of from 1° to 54.7°, and, in a cross section orthogonal to a direction along which the undulations are extended, portions at which neighboring inclined planes are brought in contact with each other are in a curve shape. The substrate is silicon or silicon carbide having a surface with a plane normal in a crystallographic <001> orientation, having {001} planes accounting for 10% or less of the entire area of the surface, etc. Also claimed is a single crystal silicon carbide having a planar defect density of 1,000/cm2 or lower, or having an internal stress of 10 MPa or lower.

Abstract: In an apparatus for vapor phase growth of silicon single crystal thin films, in-plane uniformity of susceptor temperature is improved and film thickness of a silicon single crystal thin film is uniformized. The base material of a lift pin 8 provided in a pocket 5a of a susceptor 5 is changed to a base material lower in thermal conductivity than a base material of the susceptor 5, by which local decreases in susceptor temperature in the vicinity of the lift pin are prevented. As the base material of the lift pin 8, SiC, carbon of a desired grade and quartz are preferred.

Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items, such as slurries and polishing pads, is reduced. A metal film formed on an insulating film having a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

Abstract: Etching end point judging method that includes the following steps in a dry etching end point judging method having a step of reducing noise of input signal waveforms using first digital filter, a step of obtaining a differential coefficient (primary or secondary) of a signal waveform from differential processing by operation circuit, a step of obtaining a smoothed differential coefficient value by reducing the noise components of the time series differential coefficient waveform that was obtained in the previous step, using the second digital filter, and a step of judging an etching end point by comparing the smoothed differential coefficient value and a preset value using discrimination method.

Abstract: A high-quality crystal sheet is provided. An apparatus for use in producing a crystal sheet includes a substrate having a main surface on which a crystal sheet is formed, a crucible holding a melt therein, a movable member holding the substrate to move it to bring its main surface into contact with the melt and then move the substrate away from the melt, and cooling means for cooling the movable member.

Abstract: A method for planarizing a layer of material on a semiconductor device is disclosed, which planarizes a layer on a semiconductor device using a high density plasma system, and uses a sacrificial layer having a desirable etch to deposition rate. Additionally, the method for planarizing a layer can be easily incorporated into the semiconductor fabrication process, and is capable of achieving both local and global planarization.

Abstract: An ultrasonic driver (105) is used to vibrate a filter disk (103) at ultrasonic frequencies. Vibrations are used to break up agglomerates into smaller pieces that pass through filter disk (103). The energy is controlled to minimize the translational energy given to the particles as they are broken up to prevent reagglomeration. The frequency and amplitude of the vibration is controlled to operate out of or in low energy cavitation.

Abstract: A polycrystalline silicon film 2 and tungsten silicide film 3 are formed on a silicon substrate 1. An insulating film to be a hard mask is formed on tungsten silicide film 3. A photoresist pattern 5 is formed on the insulating film. The insulating film is anisotropically etched using photoresist pattern 5 as a mask. By etching the exposed side surface of insulating film 4a in a gas phase hydrofluoric acid ambient, a hard mask 4b is formed. Thus, a mask material with a desired dimension is obtained without causing any variation in thickness of the mask material, and the layer to be the mask material is prevented from coming off the semiconductor substrate.

Abstract: A process for etching a pattern-masked conductor substrate anisotropically so as to obtain very high etch rates comprising adding a polymer-forming fluorocarbon gas and an etch gas at high flow rates to an etch chamber at etching pressures of 77 millitorr to 100 Torr using a high source power and bias power to the substrate support electrode to form a high density plasma. The gases can be added together, sequentially or alternately.

Abstract: A method for determining an endpoint during chemical-mechanical polishing of a semiconductor wafer (100, 200) is disclosed. The method comprises the steps of depositing on a first layer (106, 206) to be polished a second layer (108, 208), the physical properties of the first layer (106, 206) being different from the physical properties of the second layer (108, 208). After that, the wafer (100, 200) is polished by chemical-mechanical polishing. Due to the different physical properties of the layers, a variation of the physical properties can be detected, and an endpoint can be determined on the basis of the detected variation. Further, a semiconductor wafer for use in a chemical-mechanical polishing process is disclosed.

Abstract: There is disclosed a process for manufacturing a semiconductor device. When a metal film is formed by plasma CVD in a contact hole which penetrates an interlayer insulating film and reaches an electrode of the device, a gas comprising hydrogen and argon in a deposition chamber of a plasma CVD apparatus is introduced. Then a metal halide gas is introduced in the deposition chamber simultaneously with or before plasma generation.

Abstract: Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays are described. In one embodiment, a conductive capacitor plug is formed to extend from proximate a substrate node location to a location elevationally above all conductive material of an adjacent bit line. In another embodiment, a capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line. In another embodiment, capacitor contact openings are formed to elevationally below the bit lines after the bit lines are formed. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.

Abstract: A nitride etch process particularly useful when integrated with a silicon trench etch needing a sloping silicon surface adjacent to the interface between the silicon and an oxide layer intermediate the silicon and nitride. The nitride etch process is a plasma process having an etching gas mixture of sulfur hexafluoride (SF6) and trifluoromethane (CHF3) although nitrogen or oxygen may be added for additional controls. The trifluoromethane is believed to create a polymer passivation on the sidewalls of the hole being etched which, when the etch reaches the oxide-silicon interface, protects the interface and underlying silicon. The nitride etch may proceed through the oxide or a separate fluorocarbon-based oxide etching step may be performed before a bromine-based etch of the silicon starts.

Abstract: A method and system for determining polycrystalline silicon chunk size for use with a Czochralski silicon growing process. Polycrystalline silicon chunks are arranged on a measuring background. A camera captures an image of the chunks. An image processor processes the image and determines the dimensions of the chunks based on the captured image. A size parameter associated with the chunks is determined.