Abstract: A plasma etch process for forming a high aspect ratio contact opening through a silicon oxide layer is disclosed. The silicon oxide layer is plasma etched using etch gases that include at least one organic fluorocarbon gas. At least one etch gas is used that includes one or more nitrogen-comprising gases to deposit a surface polymeric material during the etching for maintaining a masking layer over the silicon oxide layer. The method of the invention achieves a complete and anistropic etching of a contact opening having a high aspect ratio and the desired dimensions.

Abstract: An apparatus for depositing a semiconductor film on a wafer, which is held on a holder inside a reactor, with at least one source gas supplied onto the wafer. The apparatus includes a decontamination film made of a semiconductor that contains at least one constituent element of the semiconductor film to be deposited. The decontamination film covers inner walls of the reactor, which are located upstream with respect to the source gas supplied and/or over the holder.

Abstract: A method and composition for planarizing a substrate. The composition includes one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, a polar solvent, and deionized water. The composition may further comprise one or more surfactants, one or more agents to adjust the pH and/or abrasive particles. The method comprises planarizing a substrate using a composition including a polar solvent.

Abstract: A wafer carrier used for a chemical mechanical device has a polishing head and a pad conditioner. The polishing head has a retainer ring secured to a bottom of the polishing head to hold a wafer. The pad conditioner can be fixed on a surface of the retainer ring, attached to side surfaces of the retainer ring, or embedded in the retainer ring, such that the pad conditioner and the polishing head can be integrally formed.

Abstract: A method of working a piezoelectric substance, which comprises the steps of, forming, on one surface of a piezoelectric block, an etching mask having an aperture which defines a boundary region between a first piezoelectric segment to be removed, and a second piezoelectric segment to be left remained, forming, on the opposite surface of the piezoelectric block, a sacrificial layer which corresponds to the first piezoelectric segment to be removed and the boundary region, etching the piezoelectric block in the boundary region to reach the sacrificial layer, and eliminating the sacrificial layer to remove the first piezoelectric segment.

Abstract: A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and then using the silicide 260 to mask removal of the unreacted silicon 220 and 230 in locations where the hardmask 240 had been present. The metal silicide 260 formed in the exposed silicon regions 220 and 230 functions as a self-aligned mask against the silicon 220 and 230 etching. By using a selective etching process between the silicon 220 and 230 and the silicide 260, the silicon 220 and 230 can be etched down to the gate oxide 210 to form the polycide (silicide/polysilicon) gate. The polycide gate formed by this method is particularly advantageous in DRAM applications, but can also be used as a MOS gate in a transistor.

Abstract: There is provided a dry etching method for forming an insulating layer of SiO2 or the like in a desired shape with a substantially infinite selection property with respect to Si3N4 used as an etching stopper. As an etching gas a gas (HI, or a gas having a constitution of CxHyIz) containing iodine in a molecule is added. Here, a mixing ratio (I/C) of iodine to carbon in the etching gas is 0.3≦(I/C)≦1.5. Alternatively, instead of the iodine-containing gas the gas containing chlorine or bromine as the same halogen element is used. Since iodine, chlorine, or bromine contained in the etching gas generates a low vapor pressure material on Si3N4, Si3N4 etching is completely prohibited. Since no low vapor pressure material is generated on SiO2 or SiOF as a material to be etched, a high etching rate can be obtained.

Abstract: A process for growing single crystal silicon ingots of which portions are substantially free of agglomerated intrinsic point defects. An ingot is grown generally in accordance with the Czochralski method. A first portion of the ingot cools to a temperature which is less than a temperature TA at which agglomeration of intrinsic point defects in the ingot occurs during the time the ingot is being grown, while a second portion remains at a temperature above TA. The second portion of the ingot is subsequently maintained at a temperature above TA to produce a portion which is substantially free of agglomerated intrinsic point defects.

Abstract: A furnace for growing a high volume of crystals includes a plurality of individual growth stations and first and second heater matrixes. Each individual growth station has a crucible and an insulating container generally surrounding the crucible and thermally isolating the crucible from the other individual growth stations. The first and second heater matrices each include at least two legs electrically connected in parallel and each of the legs have at least two resistance heaters electrically connected in series. Each of the individual growth stations have at least one of the resistance heaters within the first heater matrix and at least one of the resistance heaters within the second heater matrix associated therewith. The resistance heaters of the first heater matrix are located above the crucibles and are preferably adapted to provide a homogeneous temperature across tops of the crucibles.

Abstract: A plasma processing system and method wherein a power source produces a magnetic field and an electric field, and a window disposed between the power source and an interior of a plasma chamber couples the magnetic field into the plasma chamber thereby to couple power inductively into the chamber and based thereon produce a plasma in the plasma chamber. The window can be shaped and dimensioned to control an amount of power capacitively coupled to the plasma chamber by means of the electric field so that the amount of capacitively coupled power is selected in a range from zero to a predetermined amount. Also, a tuned antenna strap having r.f. power applied thereto to produce a standing wave therein can be arranged adjacent the window to couple magnetic field from a current maximum formed in the strap to the interior of the chamber.

Abstract: The object of the present invention is to provide an aqueous dispersion for chemical mechanical polishing which can be polished working film for semiconductor devices and which is useful for STI. The aqueous dispersion for chemical mechanical polishing of the invention is characterized by comprising an inorganic abrasive such as silica, ceria and the like, and organic particles composed of a resin having anionic group such as carboxyl group into the molecular chains. The removal rate for silicon oxide film is at least 5 times, particularly 10 times the removal rate for silicon nitride film. The aqueous dispersion may also contain an anionic surfactant such as potassium dodecylbenzene sulfonate and the like. And a base may also be included in the aqueous dispersion for adjustment og the pH to further enhance the dispersability, removal rate and selectivity.

Abstract: Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug.

Abstract: A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.

Abstract: A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.

Abstract: A post-etch clean up process for OSG. After the trench (112)/via (114) etch in a dual damascene process, a wet chemistry comprising HF and H2O2 is used to remove residues without etching or damaging the OSG film in the ILD (108) or IMD (110).

Abstract: There is disclosed a heat treatment method for a silicon monocrystal wafer comprising the steps of heat-treating in a reducing atmosphere a silicon monocrystal wafer manufactured by growing a silicon monocrystal ingot by Czochralski method wherein a wafer obtained from a silicon monocrystal ingot having oxygen concentration of 16 ppma or less which is manufactured by pulling at a growth rate of 0.6 mm/min or more, and in which COPs exist in high density is subjected to anneal heat treatment at 1200° C. or above for one second or more through use of a rapid heating/rapid cooling apparatus, or at 1200° C. or above for 30 minutes or more through use of a batchwise heat treatment furnace, and no defect silicon monocrystal wafer obtained with the method.

Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

Abstract: A method of forming wires for semiconductor devices can restrict increase of a wires resistance and a contact resistance of the semiconductor device by forming a plug without generating a void or keyhole, and includes a step of forming an insulation film on lower wires, a step of forming a contact hole on the lower wires by selectively etching the insulation film, a step of performing a precleaning process by using an argon sputtering method until the lower wires at the lower portion of the contact hole are etched at a predetermined depth, a step of forming a plug by depositing a tungsten in the contact hole, and a step of forming upper wires on the plug and the second insulation film. A re-deposition layer consisting of a material of the lower wires is formed at the inner walls of the contact hole in the precleaning process, and thus a whole process is simplified by omitting a step of forming a glue layer or adhesion layer.

Abstract: A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces.

Abstract: A method of minimizing repetitive chemical-mechanical polishing scratch marks from occurring on a polished semiconductor wafer surface resulting from breaking away of surface peaks having an elevation of at least 400 nanometers above an outer surface immediately adjacent said peaks comprises improving adherence of said peaks to the wafer by filling at least a portion of the volume between adjacent peaks with a material and chemical-mechanical polishing the peaks and the material at the same time. A method of minimizing undesired node-to-node shorts of a length less than or equal to 0.3 micron formed laterally along an insulating dielectric layer in a monolithic integrated circuit chip comprises depositing a sacrificial layer of material over the dielectric layer and chemical-mechanical polishing completely through the sacrificial layer and into the dielectric layer prior to depositing any metal over the insulating dielectric layer.