Abstract: A process for forming a bump via to interconnect upper and lower circuits wherein a layer of metal is etched down, leaving a bump via and a lower portion of the layer. A lower circuit pattern is then formed in the lower portion, following which the pattern and bump via are covered with an insulating layer. Smoothing then results in the top surface of the bump via being exposed such that an upper circuit can then be formed on the insulating layer and in connection with said bump via.

Abstract: A device for processing a substrate comprises a processing vessel (1), an outer vessel (2) for surrounding the processing vessel (1) which outer vessel (2) can be sealed, a first supporting member (4) for bringing the substrate (3) into and out from the processing vessel (1) which first supporting member (4) supports the substrate (3) in a standing manner, and a second supporting member (5) for transferring the substrate (3) between the first supporting member (4) which second supporting member (5) is movable up and down within the processing vessel (1). The device processes the entire surface of the substrate (3) uniformly and prevents varying in processing from occurrence.

Abstract: A thin barrier layer of undoped silicon is formed on an ARC to prevent resist poisoning and footing. The silicon layer can be removed with improved yield and high selectivity with respect to the underlying gate dielectric layer, thereby avoiding degradation of the gate dielectric layer. Embodiments include forming a silicon oxynitride ARC on a polycrystalline silicon layer overlying a silicon oxide layer, depositing a thin undoped polycrystalline or amorphous silicon barrier layer on the ARC, forming a photoresist mask on the barrier layer, etching to form a gate electrode on a gate oxide layer and removing the photoresist mask. The undoped polycrystalline or amorphous silicon barrier layer is then removed employing conventional wet or dry etching techniques with high etch selectivity to the underlying gate oxide layer, thereby avoiding degradation of the gate oxide layer.

Abstract: A method for recycling a disk having a layered structure on a glass substrate is disclosed. Initially, the disk is exposed to gaseous sulphur dioxide in a humid environment. Then, the disk is treated with hot water to remove the layered structure from the glass substrate.

Abstract: A wafer polishing apparatus 19 comprising a polishing head 3 having a retainer ring 20 provided around the periphery of a wafer W for suppressing movement of the wafer W in the radial direction during polishing. The retainer ring 20 comprises an attachment plate 21 affixed to the polishing head 3, a ceramic friction ring 22 brought into contact with a polishing pad 2, and a resin spacer 23 provided between the attachment plate 21 and the friction ring 22.

Abstract: Disclosed are a method for preparing a high performance BGA board containing a plurality of printed circuit boards in which a conductor circuit, a bonding pad electrically connected to a semiconductor chip, and an inner hole for mounting a semiconductor chip are formed, by primary- and secondary-laminating a plurality of boards. The present invention enjoys advantages in that contamination due to an outer layer surface treatment of the board laminate can be prevented, and a process for preventing a contamination of an inner hole can be omitted, and also a defective proportion can be reduced remarkably in comparison with prior arts by applying a pressure uniformly during a secondary lamination. Furthermore, a BGA board according to the invention has an ideal ball pitch and multi-fins, excellent electrical and thermal properties, also can be applied in the case of high current, and can be easily mounted on a chip.

Abstract: A method of etching silicon using a plasma generated from a gas comprising fluorine (F), oxygen (O), hydrogen (H) and carbon (C).

Abstract: The present invention provides a method of manufacturing an integrated circuit using a cleaning brush and a cleaning brush conditioning apparatus. In one embodiment, the cleaning brush conditioning apparatus comprises a conditioning bar and a load cell coupled to the conditioning bar. The load cell is configured to force the conditioning bar against the cleaning brush.

Abstract: A contact structure for establishing electrical connection with contact targets. The contact structure is formed of a contact substrate and a plurality of contactors. The contactor has a contact portion which is oriented in a vertical direction to form a contact point, an intermediate portion which is inserted in a through hole provided on the contact substrate, and a base portion having a base end which functions as a contact pad and a spring portion provided between the base end and the intermediate portion for producing a resilient contact force when the contactor is pressed against the contact target.

Abstract: An apparatus and a method for photoreducing copper oxide layers from semiconductor wafers during the processes of forming interconnects in advanced IC manufacturing. The apparatus comprises a reaction chamber with a high intensity UV light source and a wafer holder in the chamber. The UV light source is made of arrays of microdischarge devices fabricated on a semiconductor wafer where each of the microdischarge devices has the structure of a hollow cathode. Multiple arrays of microdischarge devices can be assembled together to make a planar UV lamp so as to provide a sufficient area for the UV illumination. The wafer holder in the chamber is made rotatable for a better uniformity during the photoreduction process. A non-oxidizing gas is flowed into the chamber to prevent instant and subsequent oxidation on the copper surface.

Abstract: A modular device of tubular plasma source mainly includes at least two tubular antennae, one RF power supply and one reference potential. The tubular antennae are arranged side by side for inducing plasma. Each tubular antenna includes an induction coil being a spiral spring shape, and a dielectric sleeve having a hollow through hole for putting in the induction coil. The RF power supply connects with the induction coil in parallel or in series, the reference potential refers to the RF power supply and connects with the induction coil.

Abstract: A method and apparatus is disclosed for polishing a semiconductor wafer. A polishing pad including a first surface and a semiconductor wafer including a second surface are aligned to each other. To allow alignment of an axis of rotation of the surfaces, at least one of the first and second surfaces includes an adjustable axis of rotation. After the axis of rotation of the first and second surfaces is aligned, the adjustable axis of rotation is set, preferably with a magneto-rheological fluid or similarly acting material, to maintain a fixed position. Thereafter, the polishing pad is utilized to polish the semiconductor wafer.

Abstract: A method for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth to achieve n-, i-, or p-type conductivity. In order to have growth cycles of sufficient duration, preferably an extended Ga source is used in which a portion of the Ga source is maintained at a relatively high temperature while most of the Ga source is maintained at a temperature close to, and just above, the melting temperature of Ga. To grow large boules of AlGaN, preferably multiple Al sources are used, the Al sources being sequentially activated to avoid Al source depletion and excessive degradation.

Abstract: A film forming apparatus and method of the present invention include a substrate holding section for holding a plurality of substrates in a plane within a chamber, first and second process gas discharge sections provided opposite to the substrate holding section to discharge first and second process gases, a rotation mechanism for rotating the substrate holder, and a heater for heating the substrates. While the substrates are rotating as the substrate holding section rotates, the substrate holding section, first and second mono atomic layers are alternately stacked on the corresponding substrates. A compound film is therefore formed through a reaction involved under heating.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: The present invention provides a semiconductor manufacturing method, a plasma processing method and a plasma processing apparatus for generating a plasma in a processing chamber and carrying out processing on material to be processed by using the plasma, comprising a floating-foreign-particle measuring apparatus including: a light radiating optical system for radiating a light having a desired wavelength and completing intensity modulation at a desired frequency to the processing chamber; a scattered-light detecting optical system for separating a component with the desired wavelength from scattered lights obtained from the processing chamber as a result of radiation of the light by the light radiating optical system, for optically receiving the component and for converting the component into a first signal; and a foreign-particle-signal extracting unit which separates a second signal representing foreign particle floating in the plasma or in an area in proximity to the plasma from a third signal obtained by

Abstract: A new method is provided for the polishing of semiconductor surfaces such as the surface of a substrate, the surface of deposited copper and the surface of low-k layers of dielectric. The polishing method and apparatus of the invention comprise a new slurry delivery design whereby at least two different slurries can be independently controlled and mixed for delivery to a slurry container. The slurry container is in direct physical contact with a polishing pad, providing for the mixed slurry to be distributed over the surface of the polishing pad.

Abstract: A new method is provided for creating a dual damascene structure. Two layers of dielectric are deposited in sequence. The lower layer of dielectric is the via dielectric and is selected such that it has a low etching rate (when compared with the upper layer of dielectric) and results in different volatile gas during the etch of the via. A first photoresist is patterned for the via, the etch for the via etches through both layers of dielectric. A second layer of photoresist is patterned for the trench etch, due to the difference in etch rate between the two layers of dielectric, the trench of the dual damascene structure is etched without further affecting the via etch in the lower layer of dielectric.

Abstract: A semiconductor wafer processing system for polishing a substrate that generally includes a base having a first side and a second side, and at least one drive system that is disposed on the first side of the base. One or more polishing heads are coupled to the drive system for retaining a workpiece during polishing. A first enclosure is disposed on the first side of the base and defines a first volume that includes the drive system. A second enclosure is disposed on the second side of the base and defines a second volume. A first exhaust is coupled to the second volume. When the system is coupled to a facilities exhaust or other air handler, the first exhaust ventilates the second volume. In another aspect, a method for processing a substrate is also disclosed. Generally, the method includes the steps of monitoring the flow metrics of a first exhaust from a first enclosure and a second exhaust from a second enclosure.

Abstract: A surface roughness distribution in the surface of a silicon epitaxial wafer is made uniform by optimizing a temperature distribution in the surface of a susceptor used in a vapor phase thin film growth apparatus. The susceptor is not supported by its center of the rear surface thereof, but only the peripheral portion thereof is supported using vertical pins respectively provided at the far ends of spokes radially branched from a rotary shaft. The susceptor is constituted so that a difference in temperature between the maximum and minimum in the surface of a silicon wafer is suppressed to a value equal to or less than 7° C. Hence, a surface roughness distribution in the surface of the silicon epitaxial wafer can be suppressed to a value equal to or less than 0.02 ppm.